--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: ReaderControlReg0
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-- Entity: ReaderControlReg0
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-- Date:2011-11-10
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-- Date:2011-11-10
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity ReaderControlReg1 is
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entity ReaderControlReg1 is
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port (
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port (
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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------------------ gpib --------------------
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------------------ gpib --------------------
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-- num of bytes available in fifo
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-- num of bytes available in fifo
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bytes_available_in_fifo : in std_logic_vector (10 downto 0)
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bytes_available_in_fifo : in std_logic_vector (10 downto 0)
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);
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);
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end ReaderControlReg1;
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end ReaderControlReg1;
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architecture arch of ReaderControlReg1 is
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architecture arch of ReaderControlReg1 is
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begin
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begin
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data_out(10 downto 0) <= bytes_available_in_fifo(10 downto 0);
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data_out(10 downto 0) <= bytes_available_in_fifo(10 downto 0);
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data_out(15 downto 11) <= "00000";
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data_out(15 downto 11) <= "00000";
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end arch;
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end arch;
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