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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Author: Andrzej Paluch
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-- Engineer:
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--
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--
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-- Create Date: 17:07:00 10/22/2011
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-- Create Date: 17:07:00 10/22/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: gpibCableEmulator - Behavioral
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-- Module Name: gpibCableEmulator - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity gpibCableEmulator is port (
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entity gpibCableEmulator is port (
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-- interface signals
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-- interface signals
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DIO_1 : in std_logic_vector (7 downto 0);
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DIO_1 : in std_logic_vector (7 downto 0);
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output_valid_1 : in std_logic;
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output_valid_1 : in std_logic;
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DIO_2 : in std_logic_vector (7 downto 0);
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DIO_2 : in std_logic_vector (7 downto 0);
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output_valid_2 : in std_logic;
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output_valid_2 : in std_logic;
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DIO : out std_logic_vector (7 downto 0);
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DIO : out std_logic_vector (7 downto 0);
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-- attention
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-- attention
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ATN_1 : in std_logic;
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ATN_1 : in std_logic;
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ATN_2 : in std_logic;
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ATN_2 : in std_logic;
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ATN : out std_logic;
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ATN : out std_logic;
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-- data valid
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-- data valid
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DAV_1 : in std_logic;
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DAV_1 : in std_logic;
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DAV_2 : in std_logic;
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DAV_2 : in std_logic;
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DAV : out std_logic;
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DAV : out std_logic;
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-- not ready for data
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-- not ready for data
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NRFD_1 : in std_logic;
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NRFD_1 : in std_logic;
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NRFD_2 : in std_logic;
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NRFD_2 : in std_logic;
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NRFD : out std_logic;
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NRFD : out std_logic;
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-- no data accepted
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-- no data accepted
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NDAC_1 : in std_logic;
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NDAC_1 : in std_logic;
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NDAC_2 : in std_logic;
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NDAC_2 : in std_logic;
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NDAC : out std_logic;
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NDAC : out std_logic;
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-- end or identify
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-- end or identify
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EOI_1 : in std_logic;
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EOI_1 : in std_logic;
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EOI_2 : in std_logic;
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EOI_2 : in std_logic;
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EOI : out std_logic;
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EOI : out std_logic;
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-- service request
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-- service request
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SRQ_1 : in std_logic;
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SRQ_1 : in std_logic;
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SRQ_2 : in std_logic;
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SRQ_2 : in std_logic;
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SRQ : out std_logic;
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SRQ : out std_logic;
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-- interface clear
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-- interface clear
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IFC_1 : in std_logic;
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IFC_1 : in std_logic;
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IFC_2 : in std_logic;
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IFC_2 : in std_logic;
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IFC : out std_logic;
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IFC : out std_logic;
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-- remote enable
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-- remote enable
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REN_1 : in std_logic;
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REN_1 : in std_logic;
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REN_2 : in std_logic;
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REN_2 : in std_logic;
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REN : out std_logic
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REN : out std_logic
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);
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);
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end gpibCableEmulator;
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end gpibCableEmulator;
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architecture Behavioral of gpibCableEmulator is
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architecture Behavioral of gpibCableEmulator is
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signal DIO_1_mid, DIO_2_mid : std_logic_vector (7 downto 0);
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signal DIO_1_mid, DIO_2_mid : std_logic_vector (7 downto 0);
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begin
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begin
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with output_valid_1 select DIO_1_mid <=
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with output_valid_1 select DIO_1_mid <=
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DIO_1 when '1',
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DIO_1 when '1',
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"00000000" when others;
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"00000000" when others;
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with output_valid_2 select DIO_2_mid <=
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with output_valid_2 select DIO_2_mid <=
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DIO_2 when '1',
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DIO_2 when '1',
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"00000000" when others;
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"00000000" when others;
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DIO <= not (not DIO_1_mid and not DIO_2_mid);
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DIO <= not (not DIO_1_mid and not DIO_2_mid);
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ATN <= not(not ATN_1 and not ATN_2);
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ATN <= not(not ATN_1 and not ATN_2);
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DAV <= not(not DAV_1 and not DAV_2);
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DAV <= not(not DAV_1 and not DAV_2);
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NRFD <= not(not NRFD_1 and not NRFD_2);
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NRFD <= not(not NRFD_1 and not NRFD_2);
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NDAC <= not(not NDAC_1 and not NDAC_2);
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NDAC <= not(not NDAC_1 and not NDAC_2);
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EOI <= not(not EOI_1 and not EOI_2);
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EOI <= not(not EOI_1 and not EOI_2);
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SRQ <= not(not SRQ_1 and not SRQ_2);
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SRQ <= not(not SRQ_1 and not SRQ_2);
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IFC <= not(not IFC_1 and not IFC_2);
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IFC <= not(not IFC_1 and not IFC_2);
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REN <= not(not REN_1 and not REN_2);
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REN <= not(not REN_1 and not REN_2);
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end Behavioral;
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end Behavioral;
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