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[/] [m65c02/] [trunk/] [Sim/] [tb_M65C02.v] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 98... Line 98... 
tri1    nWr;
 
tri1    nWr;
 
tri1    [ 3:0] XA;
 
tri1    [ 3:0] XA;
 
tri1    [15:0] A;
 
tri1    [15:0] A;
 
tri1    [ 7:0] DB;
 
tri1    [ 7:0] DB;
 
 
 
 
 
//tri1    nSel;
 
 
 
//tri1    SCk;
 
 
 
//tri1    MOSI;
 
 
 
//reg     MISO;
 
 
 
 
 
 
 
wire    [4:0] LED;
 
wire    [4:0] LED;
 
 
 
 
 
//  Define simulation variables
 
//  Define simulation variables
 
 
 
 
 
reg     Sim_nSO, Sim_nNMI, Sim_nIRQ;
 
reg     Sim_nSO, Sim_nNMI, Sim_nIRQ;
 
reg     [ 7:0] TestNum;
 
reg     [ 7:0] TestNum;
 
reg     [17:0] chkdad, chkadd;
 
reg     [17:0] chkdad, chkadd;
 
 
 
 
 
//integer i = 0;
 
 
 
 
 
 
 
integer cycle_cnt = 0;
 
integer cycle_cnt = 0;
 
integer instr_cnt = 0;
 
integer instr_cnt = 0;
 
 
 
 
 
integer Loop_Start = 0;
 
integer Loop_Start = 0;
 
 
 
 
 
integer Hist_File = 0;          // File handle for instruction histogram
 
integer Hist_File = 0;          // File handle for instruction histogram
 
//integer SV_Output = 0;          // File handle for State Vector Outputs
 
 
 
 
 
 
 
reg     [31:0] Hist [255:0];    // Instruction Histogram array
 
reg     [31:0] Hist [255:0];    // Instruction Histogram array
 
reg     [31:0] val;             // Instruction Histogram variable
 
reg     [31:0] val;             // Instruction Histogram variable
 
reg     [31:0] i, j;            // loop counters
 
reg     [31:0] i, j;            // loop counters
 
 
 
 
 
//reg     [((5*8) - 1):0] Op;     // Processor Mode Mnemonics String
 
 
 
//reg     [((6*8) - 1):0] Opcode; // Opcode Mnemonics String
 
 
 
//reg     [((9*8) - 1):0] AddrMd; // Addressing Mode Mnemonics String
 
 
 
 
 
 
 
// Instantiate the Unit Under Test (UUT)
 
// Instantiate the Unit Under Test (UUT)
 
 
 
 
 
M65C02  #(
 
M65C02  #(
 
            .pBootROM_File("M65C02_Tst5.txt")
 
            .pBootROM_File("Src/M65C02_Tst5.txt")
 
        ) uut (
 
        ) uut (
 
            .nRst(nRst),
 
            .nRst(nRst),
 
            .nRstO(nRstO),
 
            .nRstO(nRstO),
 
 
 
 
 
            .ClkIn(ClkIn),
 
            .ClkIn(ClkIn),
 
 
 
 
 
            .Phi1O(Phi1O),
 
            .Phi1O(Phi1O),
 
            .Phi2O(Phi2O),
 
            .Phi2O(Phi2O),
 
 
 
 
 
            .nSO(nSO),
 
 
 
            .nNMI(nNMI),
 
            .nNMI(nNMI),
 
            .nIRQ(nIRQ),
 
            .nIRQ(nIRQ),
 
            .nVP(nVP),
 
            .nVP(nVP),
 
 
 
 
 
            .BE_In(BE_In),
 
            .BE_In(BE_In),
 
            .Sync(Sync),
 
            .Sync(Sync),
 
            .nML(nML),
 
            .nML(nML),
 
 
 
 
 
            .nCE(nCE),
 
            .nCE(nCE),
 
            .RnW(RnW),
 
            .RnW(RnW),
 
            .nWr(nWr),
 
 
 
            .nOE(nOE),
 
            .nOE(nOE),
 
 
 
            .nWE(nWr),
 
            .Rdy(Rdy),
 
            .Rdy(Rdy),
 
            .XA(XA),
 
            .XA(XA),
 
            .A(A),
 
            .A(A),
 
            .DB(DB),
 
            .DB(DB),
 
 
 
 
 
            .nWP_In(1'b0),
 
            .nWP_In(1'b0),
 
 
 
 
 
            .nWait(nWait),
 
            .nWait(nWait),
 
 
 
 
 
            .LED(LED),
 
            .LED(LED)
 
 
 
 
 
            .nSel(nSel),
 
 
 
            .SCk(SCk),
 
 
 
            .MOSI(MOSI),
 
 
 
            .MISO(MISO)
 
 
 
        );
 
 
 
 
 
 
 
////  Instantiate Boot/Monitor ROM Module
 
//            .LED(LED),
 
//
 
//
 
//wire    [7:0] ROM_DO;
 
//            .nSel(nSel), 
//reg     ROM_WE;
 
//            .SCk(SCk), 
//
 
//            .MOSI(MOSI), 
//M65C02_RAM  #(
 
//            .MISO(MISO)
 
//                .pAddrSize(pRAM_AddrWidth),
 
        );
 
//                .pDataSize(8),
 
 
 
//                .pFileName("M65C02_Tst3.txt")
 
 
 
//            ) ROM (
 
 
 
//                .Clk(~Phi2O),
 
 
 
////                .Ext(1'b1),     // 4 cycle memory
 
 
 
////                .ZP(1'b0),
 
 
 
////                .Ext(1'b0),     // 2 cycle memory
 
 
 
////                .ZP(1'b0),
 
 
 
//                .Ext(1'b0),   // 1 cycle memory
 
 
 
//                .ZP(1'b1),
 
 
 
//                .WE(ROM_WE),
 
 
 
//                .AI(A[(pRAM_AddrWidth - 1):0]),
 
 
 
//                .DI(DB),
 
 
 
//                .DO(ROM_DO)
 
 
 
//            );
 
 
 
 
 
 
 
//  Instantiate RAM Module
 
//  Instantiate RAM Module
 
 
 
 
 
wire    [7:0] RAM_DO;
 
wire    [7:0] RAM_DO;
 
reg     RAM_WE;
 
reg     RAM_WE;
 
 
 
 
 
M65C02_RAM  #(
 
M65C02_RAM  #(
 
                .pAddrSize(pRAM_AddrWidth),
 
                .pAddrSize(pRAM_AddrWidth),
 
                .pDataSize(8),
 
                .pDataSize(8),
 
                .pFileName("65C02_FT.txt")
 
                .pFileName("Src/65C02_FT.txt")
 
            ) RAM (
 
            ) RAM (
 
                .Clk(~Phi2O),
 
                .Clk(~Phi2O),
 
//                .Ext(1'b1),     // 4 cycle memory
 
//                .Ext(1'b1),     // 4 cycle memory
 
//                .ZP(1'b0),
 
//                .ZP(1'b0),
 
//                .Ext(1'b0),     // 2 cycle memory
 
//                .Ext(1'b0),     // 2 cycle memory
Line 226... Line 192... 
    ClkIn    = 1;
 
    ClkIn    = 1;
 
    Sim_nSO  = 0;
 
    Sim_nSO  = 0;
 
    Sim_nNMI = 0;
 
    Sim_nNMI = 0;
 
    Sim_nIRQ = 0;
 
    Sim_nIRQ = 0;
 
    BE_In    = 1;
 
    BE_In    = 1;
 
    //Rdy      = 1;
 
 
 
    //MISO     = 1;
 
 
 
    TestNum  = 0;
 
    TestNum  = 0;
 
    chkdad   = 0;
 
    chkdad   = 0;
 
    chkadd   = 0;
 
    chkadd   = 0;
 
 
 
 
 
    // Intialize Simulation Time Format
 
    // Intialize Simulation Time Format
Line 243... Line 207... 
    for(cycle_cnt = 0; cycle_cnt < 256; cycle_cnt = cycle_cnt + 1)
 
    for(cycle_cnt = 0; cycle_cnt < 256; cycle_cnt = cycle_cnt + 1)
 
        Hist[cycle_cnt] = 0;
 
        Hist[cycle_cnt] = 0;
 
    cycle_cnt = 0;
 
    cycle_cnt = 0;
 
 
 
 
 
    Hist_File = $fopen("M65C02_Hist_File.txt", "w");
 
    Hist_File = $fopen("M65C02_Hist_File.txt", "w");
 
//    SV_Output = $fopen("M65C02_SV_Output.txt", "w");
 
 
 
 
 
 
 
    // Wait 100 ns for global reset to finish
 
    // Wait 100 ns for global reset to finish
 
 
 
 
 
    #101 nRst = 1;
 
    #101 nRst = 1;
 
 
 
 
 
    // Add stimulus here
 
 
 
 
 
 
 
    // Start the Simulation Loop
 
    // Start the Simulation Loop
 
 
 
 
 
    wait(A == pSim_Loop);
 
    wait(A == pSim_Loop);
 
    @(posedge Phi1O);
 
    @(posedge Phi1O);
 
 
 
 
Line 274... Line 235... 
                @(posedge Phi1O);
 
                @(posedge Phi1O);
 
                if(A == pSim_Loop) begin
 
                if(A == pSim_Loop) begin
 
                    @(posedge Phi1O);
 
                    @(posedge Phi1O);
 
                    @(posedge Phi1O);
 
                    @(posedge Phi1O);
 
                    @(posedge Phi1O);
 
                    @(posedge Phi1O);
 
                    $display("End of Simulation - Looping to Start detected/n");
 
 
 
                    $display("\tSuccess - All enabled tests passed.\n");
 
                    $display("\n\tTest Loop Complete\n");
 
 
 
                    $display("\tEnd of Simulation-Looping to Start detected\n");
 
 
 
                    $display("\t\tSuccess - All enabled tests passed.\n");
 
 
 
 
 
 
 
                    $fclose(Hist_File);
 
 
 
 
 
                    $stop;
 
                    $stop;
 
                end
 
                end
 
            end
 
            end
 
        end
 
        end
 
    join
 
    join
Line 315... Line 281... 
    chkadd = ((A == 16'h354E) ? (chkadd + 1) : chkadd);
 
    chkadd = ((A == 16'h354E) ? (chkadd + 1) : chkadd);
 
end
 
end
 
 
 
 
 
//  Connect ROM/RAM to M65C02 memory bus
 
//  Connect ROM/RAM to M65C02 memory bus
 
 
 
 
 
//always @(*) ROM_WE <= Phi2O &  A[15] & ~nWr;
 
 
 
always @(*) RAM_WE <= Phi2O & ~A[15] & ~nWr;
 
always @(*) RAM_WE <= Phi2O & ~A[15] & ~nWr;
 
 
 
 
 
//assign DB = ((~nOE) ? ((A[15]) ? ROM_DO : RAM_DO) : {8{1'bZ}});
 
 
 
assign DB = ((~nOE) ? RAM_DO : {8{1'bZ}});
 
assign DB = ((~nOE) ? RAM_DO : {8{1'bZ}});
 
 
 
 
 
//  Generate Simulate nIRQ signal based on writes by test program to address
 
//  Generate Simulate nIRQ signal based on writes by test program to address
 
//      0xFFF8 (assert nIRQ) or 0xFFF9 (deassert nIRQ)
 
//      0xFFF8 (assert nIRQ) or 0xFFF9 (deassert nIRQ)
 
 
 
 
Line 345... Line 309... 
 
 
 
 
always @(posedge uut.ClkGen.Clk)
 
always @(posedge uut.ClkGen.Clk)
 
begin
 
begin
 
    if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
 
    if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
 
        cycle_cnt = 0;
 
        cycle_cnt = 0;
 
    else if(Phi1O & uut.C4)
 
    else if(Phi1O & uut.Rdy)
 
        cycle_cnt = ((A == 16'h0400) ? 1 : (cycle_cnt + 1));
 
        cycle_cnt = ((A == 16'h0400) ? 1 : (cycle_cnt + 1));
 
end
 
end
 
 
 
 
 
always @(posedge uut.ClkGen.Clk)
 
always @(posedge uut.ClkGen.Clk)
 
begin
 
begin
 
    if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
 
    if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
 
        instr_cnt = 0;
 
        instr_cnt = 0;
 
    else if(Sync & Phi1O & uut.C4)
 
    else if(Sync & Phi1O & uut.Rdy)
 
        instr_cnt = ((A == 16'h0400) ? 1 : (instr_cnt + 1));
 
        instr_cnt = ((A == 16'h0400) ? 1 : (instr_cnt + 1));
 
end
 
end
 
 
 
 
 
//  Perform Instruction Histogramming for coverage puposes
 
//  Perform Instruction Histogramming for coverage puposes
 
 
 
 
 
always @(posedge uut.ClkGen.Clk)
 
always @(posedge uut.ClkGen.Clk)
 
begin
 
begin
 
//    $fstrobe(SV_Output, "%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
 
 
 
//             IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
 
 
 
 
 
 
 
    if(~(uut.ClkGen.Rst | ~uut.ClkGen.nRst)) begin
 
    if(~(uut.ClkGen.Rst | ~uut.ClkGen.nRst)) begin
 
        if(Sync & Phi2O & uut.C3) begin
 
        if(uut.Rdy & uut.uP.CE_IR) begin
 
            if((A == 16'h0400)) begin
 
            if((A == pSim_Loop)) begin
 
                if((Loop_Start == 1)) begin
 
                if((Loop_Start == 1)) begin
 
                    for(i = 0; i < 16; i = i + 1)
 
                    for(i = 0; i < 16; i = i + 1) begin     // lower nibble
 
                        for(j = 0; j < 16; j = j + 1) begin
 
                        for(j = 0; j < 16; j = j + 1) begin // upper nibble
 
                            val = Hist[(j * 16) + i];
 
                            val = Hist[(j * 16) + i];
 
                            Hist[(j * 16) + i] = 0;
 
                            Hist[(j * 16) + i] = 0;
 
                            if((j == 0))
 
                            if((j == 0) || (j == 8))
 
                                $fwrite(Hist_File, "\n%h : %h", ((j * 16) + i), val);
 
                                $fwrite(Hist_File, "\n%h : %d", (j*16)+i, val);
 
                            else
 
                            else
 
                                $fwrite(Hist_File, " %h", val);
 
                                $fwrite(Hist_File, " %d", val);
 
 
 
                        end
 
                        end
 
                        end
 
                    $fclose(Hist_File);
 
 
 
//                    $fclose(SV_Output);
 
 
 
 
 
 
 
                    $display("\nTest Loop Complete\n");
 
 
 
 
 
 
 
//                    $stop;
 
 
 
                end else begin
 
                end else begin
 
                    Loop_Start = 1;
 
                    Loop_Start = 1;
 
                end
 
                end
 
            end
 
            end
 
            val      = Hist[DB];
 
            val             = Hist[uut.uP.DI];
 
            Hist[DB] = val + 1;
 
            Hist[uut.uP.DI] = val + 1;
 
        end
 
        end
 
    end
 
    end
 
end
 
end
 
 
 
 
 
////  Test Monitor System Function
 
 
 
//
 
 
 
//always @(posedge Phi1O)
 
 
 
//begin
 
 
 
//    $monitor("%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
 
 
 
//             IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
 
 
 
//end
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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