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`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// 4004 CPU Integration Module
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// are NOT "public domain" and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module i4004(
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input wire sysclk,
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input wire clk1_pad,
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input wire clk2_pad,
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input wire poc_pad,
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input wire test_pad,
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inout wire [3:0] data_pad,
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output wire cmrom_pad,
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output wire cmram0_pad,
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output wire cmram1_pad,
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output wire cmram2_pad,
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output wire cmram3_pad,
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output wire sync_pad
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);
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// Common BiDir data bus
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wire [3:0] data;
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// Timing and I/O Board Outputs
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wire clk1;
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wire clk2;
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wire a12;
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wire a22;
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wire a32;
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wire m12;
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wire m22;
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wire x12;
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wire x22;
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wire x32;
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wire gate;
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wire poc; // Clean POC_PAD
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wire n0432; // Clean TEST_PAD
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// Outputs from the Instruction Decode board
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wire jcn_isz;
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wire jin_fin;
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wire jun_jms;
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wire cn_n;
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wire bbl;
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wire jms;
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wire sc;
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wire dc;
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wire n0636;
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wire sc_m22_clk2;
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wire fin_fim_src_jin;
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wire inc_isz_add_sub_xch_ld;
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wire inc_isz_xch;
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wire opa0_n;
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wire cma;
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wire write_acc_1;
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wire write_carry_2;
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wire read_acc_3;
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wire add_group_4;
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wire inc_group_5;
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wire sub_group_6;
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wire ior;
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wire iow;
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wire ral;
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wire rar;
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wire ope_n;
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wire daa;
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wire dcl;
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wire inc_isz;
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wire kbp;
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wire o_ib;
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wire tcs;
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wire xch;
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wire n0342;
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wire x21_clk2;
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wire x31_clk2;
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wire com_n;
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// Outputs from the ALU board
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wire acc_0;
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wire add_0;
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wire cy_1;
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wire cmram0;
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wire cmram1;
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wire cmram2;
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wire cmram3;
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wire cmrom;
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// Instantiate the Timing and I/O board
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timing_io tio_board (
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.sysclk(sysclk),
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.clk1_pad(clk1_pad),
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.clk2_pad(clk2_pad),
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.poc_pad(poc_pad),
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.ior(ior),
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.clk1(clk1),
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.clk2(clk2),
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.a12(a12),
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.a22(a22),
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.a32(a32),
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.m12(m12),
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.m22(m22),
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.x12(x12),
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.x22(x22),
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.x32(x32),
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.gate(gate),
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.poc(poc),
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.data(data),
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.data_pad(data_pad),
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.test_pad(test_pad),
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.n0432(n0432),
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.sync_pad(sync_pad),
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.cmrom(cmrom),
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.cmrom_pad(cmrom_pad),
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.cmram0(cmram0),
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.cmram0_pad(cmram0_pad),
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.cmram1(cmram1),
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.cmram1_pad(cmram1_pad),
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.cmram2(cmram2),
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.cmram2_pad(cmram2_pad),
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.cmram3(cmram3),
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.cmram3_pad(cmram3_pad)
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);
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// Instantiate the Instruction Decode board
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instruction_decode id_board (
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.sysclk(sysclk),
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.clk1(clk1),
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.clk2(clk2),
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.a22(a22),
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.m12(m12),
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.m22(m22),
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.x12(x12),
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.x22(x22),
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.x32(x32),
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.poc(poc),
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.n0432(n0432),
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.data(data),
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.jcn_isz(jcn_isz),
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.jin_fin(jin_fin),
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.jun_jms(jun_jms),
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.cn_n(cn_n),
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.bbl(bbl),
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.jms(jms),
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.sc(sc),
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.dc(dc),
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.n0636(n0636),
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.sc_m22_clk2(sc_m22_clk2),
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.fin_fim_src_jin(fin_fim_src_jin),
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.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
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.inc_isz_xch(inc_isz_xch),
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.opa0_n(opa0_n),
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.acc_0(acc_0),
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.add_0(add_0),
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.cy_1(cy_1),
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.cma(cma),
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.write_acc_1(write_acc_1),
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.write_carry_2(write_carry_2),
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.read_acc_3(read_acc_3),
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.add_group_4(add_group_4),
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.inc_group_5(inc_group_5),
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.sub_group_6(sub_group_6),
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.ior(ior),
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.iow(iow),
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.ral(ral),
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.rar(rar),
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.ope_n(ope_n),
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.daa(daa),
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.dcl(dcl),
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.inc_isz(inc_isz),
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.kbp(kbp),
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.o_ib(o_ib),
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.tcs(tcs),
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.xch(xch),
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.n0342(n0342),
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.x21_clk2(x21_clk2),
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.x31_clk2(x31_clk2),
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.com_n(com_n)
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);
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// Instantiate the ALU board
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alu alu_board (
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.sysclk(sysclk),
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.a12(a12),
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.m12(m12),
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.x12(x12),
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.poc(poc),
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.data(data),
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.acc_0(acc_0),
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.add_0(add_0),
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.cy_1(cy_1),
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.cma(cma),
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.write_acc_1(write_acc_1),
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.write_carry_2(write_carry_2),
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.read_acc_3(read_acc_3),
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.add_group_4(add_group_4),
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.inc_group_5(inc_group_5),
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.sub_group_6(sub_group_6),
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.ior(ior),
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.iow(iow),
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.ral(ral),
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.rar(rar),
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.ope_n(ope_n),
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.daa(daa),
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.dcl(dcl),
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.inc_isz(inc_isz),
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.kbp(kbp),
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.o_ib(o_ib),
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.tcs(tcs),
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.xch(xch),
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.n0342(n0342),
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.x21_clk2(x21_clk2),
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.x31_clk2(x31_clk2),
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.com_n(com_n),
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.cmram0(cmram0),
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.cmram1(cmram1),
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.cmram2(cmram2),
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.cmram3(cmram3),
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.cmrom(cmrom)
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);
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// Instantiate the Instruction Pointer board
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instruction_pointer ip_board (
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.sysclk(sysclk),
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.clk1(clk1),
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.clk2(clk2),
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.a12(a12),
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.a22(a22),
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.a32(a32),
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.m12(m12),
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.m22(m22),
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.x12(x12),
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.x22(x22),
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.x32(x32),
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.poc(poc),
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.m12_m22_clk1_m11_m12(gate),
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.data(data),
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.jcn_isz(jcn_isz),
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.jin_fin(jin_fin),
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.jun_jms(jun_jms),
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.cn_n(cn_n),
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.bbl(bbl),
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.jms(jms),
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.sc(sc),
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.dc(dc)
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);
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// Instantiate the Scratchpad board
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scratchpad sp_board (
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.sysclk(sysclk),
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.clk1(clk1),
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.clk2(clk2),
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.a12(a12),
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.a22(a22),
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.a32(a32),
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.m12(m12),
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.m22(m22),
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.x12(x12),
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.x22(x22),
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.x32(x32),
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.poc(poc),
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.m12_m22_clk1_m11_m12(gate),
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.data(data),
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.n0636(n0636),
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.sc_m22_clk2(sc_m22_clk2),
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.fin_fim_src_jin(fin_fim_src_jin),
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.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
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.inc_isz_xch(inc_isz_xch),
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.opa0_n(opa0_n),
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.sc(sc),
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.dc(dc)
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);
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endmodule
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No newline at end of file
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No newline at end of file
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