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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [instruction_decode.v] - Diff between revs 5 and 6

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// 4004 Instruction Decoder
// 4004 Instruction Decoder
// 
// 
// This file is part of the MCS-4 project hosted at OpenCores:
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
//      http://www.opencores.org/cores/mcs-4/
// 
// 
// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
// 
// 
// These materials are provided under the Creative Commons
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
// are NOT "public domain" and are protected by copyright.
// They are NOT "public domain", and are protected by copyright.
// 
// 
// This work based on materials provided by Intel Corporation and
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// others under the same license. See the file doc/License for
// details of this license.
// details of this license.
//
//
Line 178... Line 178...
        reg  n0405;
        reg  n0405;
        always @(posedge sysclk) begin
        always @(posedge sysclk) begin
                if (clk2)
                if (clk2)
                        n0405 <= n0413;
                        n0405 <= n0413;
        end
        end
        always @(posedge sysclk) begin
    always @(*) begin
                if (clk1)
                if (clk1)
                        n0397 <= ~n0405;
                        n0397 <= ~n0405;
        end
        end
        assign cn_n = ~n0397;
        assign cn_n = ~n0397;
 
 

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