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// 4004 Timing and I/O Interfaces
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// 4004 Timing and I/O Interfaces
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//
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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// http://www.opencores.org/cores/mcs-4/
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//
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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//
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// These materials are provided under the Creative Commons
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// are NOT "public domain" and are protected by copyright.
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// They are NOT "public domain", and are protected by copyright.
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//
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//
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// This work based on materials provided by Intel Corporation and
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// others under the same license. See the file doc/License for
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// details of this license.
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// details of this license.
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//
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//
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// External I/O Pad conditioning
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// External I/O Pad conditioning
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inout wire [3:0] data,
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inout wire [3:0] data,
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inout wire [3:0] data_pad,
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inout wire [3:0] data_pad,
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input wire test_pad,
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input wire test_pad,
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output reg n0432,
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output reg n0432,
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output reg sync_pad,
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output wire sync_pad,
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input wire cmrom,
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input wire cmrom,
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output wire cmrom_pad,
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output wire cmrom_pad,
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input wire cmram0,
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input wire cmram0,
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output wire cmram0_pad,
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output wire cmram0_pad,
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input wire cmram1,
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input wire cmram1,
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assign cmram2_pad = cmram2;
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assign cmram2_pad = cmram2;
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assign cmram3_pad = cmram3;
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assign cmram3_pad = cmram3;
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// Generate the 8 execution phase indicators
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// Generate the 8 execution phase indicators
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reg [0:7] master = 8'h00;
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timing_generator timing_generator (
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reg [0:7] slave = 8'h00;
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.sysclk (sysclk),
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always @(posedge sysclk) begin
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.clk1 (clk1),
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if (clk2)
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.clk2 (clk2),
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master <= {~|slave[0:6], slave[0:6]};
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.a12 (a12),
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else
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.a22 (a22),
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sync_pad <= master[7];
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.a32 (a32),
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.m12 (m12),
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if (clk1)
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.m22 (m22),
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slave <= master;
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.x12 (x12),
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end
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.x22 (x22),
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.x32 (x32),
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assign a12 = slave[0];
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.sync (sync_pad)
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assign a22 = slave[1];
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);
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assign a32 = slave[2];
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assign m12 = slave[3];
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assign m22 = slave[4];
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assign x12 = slave[5];
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assign x22 = slave[6];
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assign x32 = slave[7];
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// Generate the DRAM Input Gate signal
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// Generate the DRAM Input Gate signal
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// Properly called M12+M22+CLK1~(M11&M12)
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// Properly called M12+M22+CLK1~(M11&M12)
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wire n0279 = ~(a32 | m12);
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wire n0279 = ~(a32 | m12);
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reg n0278;
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reg n0278;
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wire n0708 = ~((n0278 & clk1) | m12 | m22);
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wire n0708 = ~((n0278 & clk1) | m12 | m22);
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assign gate = ~n0708;
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assign gate = ~n0708;
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// Generate a clean POC signal
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// Generate a clean POC signal
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always @(posedge sysclk) begin
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always @(posedge sysclk or posedge poc_pad) begin
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if (poc_pad) poc <= 1'b1;
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if (poc_pad) poc <= 1'b1;
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else if (a12) poc <= 1'b0;
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else if (a12) poc <= 1'b0;
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else poc <= poc;
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end
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end
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// Generate a clean ~TEST signal (n0432)
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// Generate a clean ~TEST signal (n0432)
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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n0432 <= ~test_pad;
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n0432 <= ~test_pad;
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