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# Classic-MIPS
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A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a 1024 depth branch prediction buffer, a 2KB direct-mapped cache and a 64K main memory. You can also download the project from "https://github.com/valar1234/MIPS" if the SVN access is not available.
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A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
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This MIPS processor is coded according to the fifth edition book of David A.Patternson & John L.Hennsessy, "Computer Organization and Design". The architecture is the referred to the descriptions in this book.
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This MIPS processor is coded according to the fifth edition book of David A.Patternson & John L.Hennsessy, "Computer Organization and Design". The architecture is the referred to the descriptions in this book. However, some alteration are made to reduce the critical data path, especially the Forwarding in EXECUTE stage. The bypass unit are migrated from the EXECUTE stage to the DECODE stage to improve timing.
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This MIPS is fully evaluated on Xilinx Vivado design tools and several testbenchs are providered to test the processor. It is also evaluated on Xilinx ZC706 board.
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This MIPS is fully evaluated on Xilinx Vivado design tools and several testbenchs are providered to test the processor. It is also evaluated on Xilinx ZC706 board. The clock can run at 285MHz(3.5ns) and the hardware resource utilization:
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FF: 1709, LUT: 3171, MEMORY LUT: 1015, BRAM: 7.5.
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1: Classic 5-stage pipeline, including FETCH, DECODE, EXECUTE, MEM and WB.
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1: Classic 5-stage pipeline, including FETCH, DECODE, EXECUTE, MEM and WB.
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2: Apply the Dynamic Branch Prediction technology to improve the branch accuracy. It contains a 2-bit branch predictor and a 1024 depth branch prediction buffer to predict the branch address. Furthermore, it takes the jump instruction(j, jal, jr .etc) as specital branch instructions to deal with, and this can simplfy the jump implementation.
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2: Apply the Dynamic Branch Prediction technology to improve the branch accuracy. It contains a 2-bit branch predictor and a 1024 depth branch prediction buffer to predict the branch address. Furthermore, it takes the jump instruction(j, jal, jr .etc) as specital branch instructions to deal with, and this can simplfy the jump implementation.
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3: Implement the Forwarding and Stalling mechanism to solve the data-hazard.
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3: Implement the Forwarding and Stalling mechanism to solve the data-hazard.
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4: A 2KB direct-mapped data-cache is added to accelerate memory access. This cache has 64 blocks and each block has 8 words. A cache controller is designed to connect the MIPS processor and the 64KB main memory. The cache is implemented as LUT in Xilinx FPGAs, and the main memory is implemented as Block Rams(BRAM).
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4: A 2KB direct-mapped data-cache is added to accelerate memory access. This cache has 64 blocks and each block has 8 words. A cache controller is designed to connect the MIPS processor and the 64KB main memory. The cache is implemented as LUT in Xilinx FPGAs, and the main memory is implemented as Block Rams(BRAM).
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This MIPS processor supports the basic instruction as bellow:
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This MIPS processor supports the basic instructions as bellow. Users can add extra instructions conveniently.
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1 TYPE-R: AND, OR, ADD, SUB, SLT, NOR, SLRV, SLLV
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1 TYPE-R: AND, OR, ADD, SUB, SLT, NOR, SLRV, SLLV
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2 TYPE-I: ADDI, ANDI, ORI, XORI, LUI
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2 TYPE-I: ADDI, ANDI, ORI, XORI, LUI
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3 finonacci: calculate the Fibonacci series.
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3 finonacci: calculate the Fibonacci series.
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4 gcd: calculate the gcd of two numbers
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4 gcd: calculate the gcd of two numbers
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5 function/fact: test the function recursion. Accumulate the result in recursively way.
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5 function/fact: test the function recursion. Accumulate the result in recursively way.
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Any problems or bugs, please contact jfjin14@fudan.edu.cn.
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