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Instruction Decoder
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Instruction Decoder
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:copyright: Copyright (c) 2010 Jian Luo
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:license: LGPL, see LICENSE for details
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:revision: $Id: decoder.py 5 2010-11-21 10:59:30Z rockee $
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:revision: $Id: decoder.py 6 2010-11-21 23:18:44Z rockee $
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"""
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"""
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from random import randrange
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from random import randrange
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from myhdl import *
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from myhdl import *
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from defines import *
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from defines import *
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from functions import *
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from functions import *
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from gprf import *
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from gprf import *
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from debug import *
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#from debug import *
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def Decoder(
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def Decoder(
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# Inputs
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# Inputs
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clock,
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clock,
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reset,
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reset,
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Line 59... |
# Write back stage outputs
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# Write back stage outputs
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of_fwd_mem_result,
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of_fwd_mem_result,
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of_fwd_reg_d,
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of_fwd_reg_d,
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of_fwd_reg_write,
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of_fwd_reg_write,
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# XXX: if __debug__:
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# Ports only for debug
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#of_instruction=False,
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of_instruction=0,
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):
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):
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"""
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"""
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Python System Model of the OF Stage
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Python System Model of the OF Stage
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"""
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"""
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of_comb_r_has_imm_high = Signal(False)
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of_comb_r_has_imm_high = Signal(False)
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Line 176... |
#if cfg_reg_fwd_wrb == True:
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#if cfg_reg_fwd_wrb == True:
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of_fwd_mem_result.next = wb_dat_d
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of_fwd_mem_result.next = wb_dat_d
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of_fwd_reg_d.next = mm_reg_d
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of_fwd_reg_d.next = mm_reg_d
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of_fwd_reg_write.next = mm_reg_write
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of_fwd_reg_write.next = mm_reg_write
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#if __debug__:
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#if 0: # DEBUG_VERBOSE:
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#print 'OF reged:', of_reg_write, of_reg_d,' ra:', of_reg_a
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#print 'OF reged pc:', of_r_program_counter
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#print 'OF rd:', mm_reg_write, mm_reg_d, wb_dat_d,
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#print ' ra:', imem_data_in[21:16]
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#print 'OF pc:', of_comb_program_counter
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@always_comb
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@always_comb
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def regout():
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def regout():
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of_hazard.next = of_r_hazard
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of_hazard.next = of_r_hazard
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of_mem_read.next = of_r_mem_read
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of_mem_read.next = of_r_mem_read
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of_reg_d.next = of_r_reg_d
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of_reg_d.next = of_r_reg_d
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#if __debug__:
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if __debug__:
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#of_instruction.next = of_r_instruction
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of_instruction.next = of_r_instruction
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@always_comb
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@always_comb
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def comb():
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def comb():
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# XXX intbvs should be explicitly declared
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# XXX intbvs should be explicitly declared
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# Register
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# Register
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Line 195... |
r_program_counter = intbv(0)[CFG_IMEM_SIZE:]
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r_program_counter = intbv(0)[CFG_IMEM_SIZE:]
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r_program_counter[:] = if_program_counter
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r_program_counter[:] = if_program_counter
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r_immediate_high = intbv(0)[16:]
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r_immediate_high = intbv(0)[16:]
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r_has_imm_high = False
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r_has_imm_high = False
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r_reg_d = intbv(0)[5:]
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r_reg_d = intbv(0)[5:]
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# Local
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# Local Variables
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r_hazard = False
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r_hazard = False
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immediate = intbv(0)[32:]
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immediate = intbv(0)[32:]
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#r_immediate_high = intbv(0)[16:]
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immediate_low = intbv(0)[16:]
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immediate_low = intbv(0)[16:]
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instruction = intbv(0)[32:]
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instruction = intbv(0)[32:]
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mem_result = intbv(0)[32:]
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mem_result = intbv(0)[32:]
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opcode = intbv(0)[6:]
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opcode = intbv(0)[6:]
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opgroup = intbv(0)[5:]
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opgroup = intbv(0)[5:]
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Line 210... |
reg_b = intbv(0)[5:]
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reg_b = intbv(0)[5:]
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if mm_mem_read:
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if mm_mem_read:
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mem_result[:] = align_mem_load(dmem_data_in, mm_transfer_size,
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mem_result[:] = align_mem_load(dmem_data_in, mm_transfer_size,
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mm_alu_result[2:])
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mm_alu_result[2:])
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#print 'of: load %x' % mem_result
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else:
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else:
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mem_result[:] = mm_alu_result
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mem_result[:] = mm_alu_result
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wb_dat_d.next = mem_result
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wb_dat_d.next = mem_result
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Line 481... |
if __name__ == '__main__':
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if __name__ == '__main__':
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clock = Signal(False)
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clock = Signal(False)
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reset = Signal(False)
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reset = Signal(False)
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enable = Signal(False)
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enable = Signal(False)
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dmem_data_in = Signal(intbv(0)[32:])
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dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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imem_data_in = Signal(intbv(0)[32:])
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imem_data_in = Signal(intbv(0)[CFG_IMEM_WIDTH:])
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if_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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if_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_flush_id = Signal(False)
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ex_flush_id = Signal(False)
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mm_alu_result = Signal(intbv(0)[32:])
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mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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mm_mem_read = Signal(False)
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mm_mem_read = Signal(False)
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mm_reg_d = Signal(intbv(0)[5:])
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mm_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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mm_reg_write = Signal(False)
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mm_reg_write = Signal(False)
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mm_transfer_size = Signal(transfer_size_type.WORD)
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mm_transfer_size = Signal(transfer_size_type.WORD)
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gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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Line 501... |
of_branch_cond = Signal(branch_condition.NOP)
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of_branch_cond = Signal(branch_condition.NOP)
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of_carry = Signal(carry_type.C_ZERO)
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of_carry = Signal(carry_type.C_ZERO)
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of_carry_keep = Signal(False)
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of_carry_keep = Signal(False)
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of_delay = Signal(False)
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of_delay = Signal(False)
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of_hazard = Signal(False)
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of_hazard = Signal(False)
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of_immediate = Signal(intbv(0)[32:])
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of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_mem_read = Signal(False)
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of_mem_read = Signal(False)
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of_mem_write = Signal(False)
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of_mem_write = Signal(False)
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of_operation = Signal(False)
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of_operation = Signal(False)
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of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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of_reg_a = Signal(intbv(0)[5:])
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of_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_b = Signal(intbv(0)[5:])
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of_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_d = Signal(intbv(0)[5:])
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of_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_write = Signal(False)
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of_reg_write = Signal(False)
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of_transfer_size = Signal(transfer_size_type.WORD)
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of_transfer_size = Signal(transfer_size_type.WORD)
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of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_fwd_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_fwd_reg_write = Signal(False)
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if __debug__:
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of_instruction = Signal(intbv(0)[CFG_IMEM_WIDTH:])
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# End Ports only for debug
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kw = dict(
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kw = dict(
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Decoder,
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clock=clock,
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clock=clock,
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reset=reset,
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reset=reset,
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enable=enable,
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enable=enable,
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dmem_data_in=dmem_data_in,
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dmem_data_in=dmem_data_in,
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imem_data_in=imem_data_in,
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imem_data_in=imem_data_in,
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Line 553... |
of_reg_a=of_reg_a,
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of_reg_a=of_reg_a,
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of_reg_b=of_reg_b,
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of_reg_b=of_reg_b,
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of_reg_d=of_reg_d,
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of_reg_d=of_reg_d,
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of_reg_write=of_reg_write,
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of_reg_write=of_reg_write,
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of_transfer_size=of_transfer_size,
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of_transfer_size=of_transfer_size,
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of_fwd_mem_result=of_fwd_mem_result,
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of_fwd_reg_d=of_fwd_reg_d,
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of_fwd_reg_write=of_fwd_reg_write,
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)
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)
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toVerilog(**kw)
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toVerilog(Decoder, **kw)
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toVHDL(**kw)
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toVHDL(Decoder, **kw)
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### EOF ###
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### EOF ###
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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