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Execute Unit
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Execute Unit
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:copyright: Copyright (c) 2010 Jian Luo
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:license: LGPL, see LICENSE for details
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:revision: $Id: execute.py 5 2010-11-21 10:59:30Z rockee $
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:revision: $Id: execute.py 6 2010-11-21 23:18:44Z rockee $
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"""
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"""
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from myhdl import *
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from myhdl import *
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from defines import *
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from defines import *
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from functions import *
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from functions import *
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from debug import *
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def ExecuteUnit(
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def ExecuteUnit(
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# Inputs
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# Inputs
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clock,
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clock,
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reset,
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reset,
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Line 64... |
Line 63... |
ex_mem_read,
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ex_mem_read,
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ex_mem_write,
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ex_mem_write,
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ex_program_counter,
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ex_program_counter,
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ex_transfer_size,
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ex_transfer_size,
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# Generic Parameters
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# Ports only for debug
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#CFG_IMEM_SIZE=16,
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of_instruction=0,
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#CFG_DMEM_WIDTH=32,
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ex_dat_a=0,
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ex_dat_b=0,
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# XXX: if __debug__:
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ex_instruction=0,
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#of_instruction,
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ex_reg_a=0,
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#ex_dat_a,
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ex_reg_b=0,
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#ex_dat_b,
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#ex_instruction,
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#ex_reg_a,
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#ex_reg_b,
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):
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):
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"""
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"""
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"""
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"""
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ex_r_carry = Signal(False)
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ex_r_carry = Signal(False)
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ex_r_flush_ex= Signal(False)
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ex_r_flush_ex= Signal(False)
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ex_r_alu_result = Signal(intbv(0)[32:])
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ex_r_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_r_reg_d = Signal(intbv(0)[5:])
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ex_r_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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ex_r_reg_write = Signal(False)
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ex_r_reg_write = Signal(False)
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ex_comb_r_carry = Signal(False)
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ex_comb_r_carry = Signal(False)
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ex_comb_r_flush_ex = Signal(False)
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ex_comb_r_flush_ex = Signal(False)
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ex_comb_r_alu_result = Signal(intbv(0)[32:])
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ex_comb_r_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_comb_r_reg_d = Signal(intbv(0)[5:])
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ex_comb_r_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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ex_comb_r_reg_write = Signal(False)
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ex_comb_r_reg_write = Signal(False)
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ex_comb_branch = Signal(False)
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ex_comb_branch = Signal(False)
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ex_comb_dat_d = Signal(intbv(0)[32:])
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ex_comb_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_comb_flush_id = Signal(False)
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ex_comb_flush_id = Signal(False)
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ex_comb_mem_read = Signal(False)
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ex_comb_mem_read = Signal(False)
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ex_comb_mem_write = Signal(False)
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ex_comb_mem_write = Signal(False)
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ex_comb_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_comb_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_comb_transfer_size = Signal(transfer_size_type.WORD)
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ex_comb_transfer_size = Signal(transfer_size_type.WORD)
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#if __debug__:
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if __debug__:
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#ex_comb_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_comb_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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#ex_comb_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_comb_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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#ex_comb_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_comb_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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#ex_comb_reg_a = Signal(intbv(0)[5:])
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ex_comb_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
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#ex_comb_reg_b = Signal(intbv(0)[5:])
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ex_comb_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
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@always_comb
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@always_comb
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def regout():
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def regout():
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ex_alu_result.next = ex_r_alu_result
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ex_alu_result.next = ex_r_alu_result
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ex_reg_d.next = ex_r_reg_d
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ex_reg_d.next = ex_r_reg_d
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ex_reg_write.next = ex_r_reg_write
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ex_reg_write.next = ex_r_reg_write
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cpu_clock = 0
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cpu_clock = 0
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@always(clock.posedge)
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@always(clock.posedge)
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def seq():
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def seq():
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"""
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ExecUnit sequential logic
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"""
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if reset:
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if reset:
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ex_r_carry.next = False
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ex_r_carry.next = False
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ex_r_flush_ex.next = False
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ex_r_flush_ex.next = False
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ex_r_alu_result.next = intbv(0)[32:]
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ex_r_alu_result.next = intbv(0)[CFG_DMEM_WIDTH:]
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ex_r_reg_d.next = intbv(0)[5:]
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ex_r_reg_d.next = intbv(0)[CFG_GPRF_SIZE:]
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ex_r_reg_write.next = False
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ex_r_reg_write.next = False
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ex_branch.next = False
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ex_branch.next = False
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ex_dat_d.next = intbv(0)[32:]
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ex_dat_d.next = intbv(0)[CFG_DMEM_WIDTH:]
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ex_flush_id.next = False
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ex_flush_id.next = False
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ex_mem_read.next = False
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ex_mem_read.next = False
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ex_mem_write.next = False
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ex_mem_write.next = False
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ex_program_counter.next = intbv(0)[CFG_IMEM_SIZE:]
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ex_program_counter.next = intbv(0)[CFG_IMEM_SIZE:]
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ex_transfer_size.next = transfer_size_type.WORD
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ex_transfer_size.next = transfer_size_type.WORD
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Line 147... |
ex_mem_read.next = ex_comb_mem_read
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ex_mem_read.next = ex_comb_mem_read
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ex_mem_write.next = ex_comb_mem_write
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ex_mem_write.next = ex_comb_mem_write
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ex_program_counter.next = ex_comb_program_counter
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ex_program_counter.next = ex_comb_program_counter
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ex_transfer_size.next = ex_comb_transfer_size
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ex_transfer_size.next = ex_comb_transfer_size
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#if __debug__:
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if __debug__:
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#if enable:
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if enable:
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#ex_dat_a.next = ex_comb_dat_a
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ex_dat_a.next = ex_comb_dat_a
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#ex_dat_b.next = ex_comb_dat_b
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ex_dat_b.next = ex_comb_dat_b
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#ex_instruction.next = ex_comb_instruction
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ex_instruction.next = ex_comb_instruction
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#ex_reg_a.next = ex_comb_reg_a
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ex_reg_a.next = ex_comb_reg_a
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#ex_reg_b.next = ex_comb_reg_b
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ex_reg_b.next = ex_comb_reg_b
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@always_comb
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@always_comb
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def comb():
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def comb():
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"""
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ExecUnit combinatorial logic
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"""
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# Signals mapping
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# Signals mapping
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r_carry = False
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r_carry = False
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r_flush_ex = False
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r_flush_ex = False
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r_alu_result = intbv(0)[CFG_DMEM_WIDTH:]
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r_alu_result = intbv(0)[CFG_DMEM_WIDTH:]
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r_reg_d = intbv(0)[5:]
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r_reg_d = intbv(0)[CFG_GPRF_SIZE:]
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r_reg_write = False
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r_reg_write = False
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branch = False
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branch = False
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dat_d = intbv(0)[CFG_DMEM_WIDTH:]
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dat_d = intbv(0)[CFG_DMEM_WIDTH:]
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flush_id = False
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flush_id = False
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Line 324... |
result[:] = concat(False, sign_extend16(alu_src_a, alu_src_a[15]))
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result[:] = concat(False, sign_extend16(alu_src_a, alu_src_a[15]))
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#result[:] = concat(False, sign_extend(alu_src_a, alu_src_a[15],
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#result[:] = concat(False, sign_extend(alu_src_a, alu_src_a[15],
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#16, CFG_DMEM_WIDTH))
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#16, CFG_DMEM_WIDTH))
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else:
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else:
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result[:] = 0
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result[:] = 0
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#if __debug__:
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if __debug__:
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#assert False, 'FATAL Error: Unsupported ALU operation'
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assert False, 'FATAL Error: Unsupported ALU operation'
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# Set carry register
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# Set carry register
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if of_carry_keep:
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if of_carry_keep:
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r_carry = bool(ex_r_carry) # bool() needs for signal type mismatch
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r_carry = bool(ex_r_carry) # bool() needs for signal type mismatch
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else:
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else:
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Line 354... |
Line 355... |
else:
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else:
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branch = False
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branch = False
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# Handle CMPU
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# Handle CMPU
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cmp_cond = alu_src_a[CFG_DMEM_WIDTH-1] ^ alu_src_b[CFG_DMEM_WIDTH-1]
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cmp_cond = alu_src_a[CFG_DMEM_WIDTH-1] ^ alu_src_b[CFG_DMEM_WIDTH-1]
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if of_operation and cmp_cond:
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if of_operation and bool(cmp_cond):
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## Set MSB
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## Set MSB
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msb = alu_src_a[CFG_DMEM_WIDTH-1]
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msb = alu_src_a[CFG_DMEM_WIDTH-1]
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r_alu_result[:] = concat(msb, result[CFG_DMEM_WIDTH-1:])
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r_alu_result[:] = concat(msb, result[CFG_DMEM_WIDTH-1:])
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else:
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else:
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r_alu_result[:] = result[CFG_DMEM_WIDTH:]
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r_alu_result[:] = result[CFG_DMEM_WIDTH:]
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Line 384... |
ex_comb_mem_read.next = mem_read
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ex_comb_mem_read.next = mem_read
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ex_comb_mem_write.next = mem_write
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ex_comb_mem_write.next = mem_write
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ex_comb_program_counter.next = program_counter
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ex_comb_program_counter.next = program_counter
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ex_comb_transfer_size.next = transfer_size
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ex_comb_transfer_size.next = transfer_size
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#if __debug__:
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if __debug__:
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#ex_comb_dat_a.next = dat_a
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ex_comb_dat_a.next = dat_a
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#ex_comb_dat_b.next = dat_b
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ex_comb_dat_b.next = dat_b
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#ex_comb_instruction.next = of_instruction
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ex_comb_instruction.next = of_instruction
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#ex_comb_reg_a.next = of_reg_a
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ex_comb_reg_a.next = of_reg_a
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#ex_comb_reg_b.next = of_reg_b
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ex_comb_reg_b.next = of_reg_b
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return instances()
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return instances()
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if __name__ == '__main__':
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if __name__ == '__main__':
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clock = Signal(False)
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clock = Signal(False)
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reset = Signal(False)
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reset = Signal(False)
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enable = Signal(False)
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enable = Signal(False)
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dmem_data_in = Signal(intbv(0)[32:])
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dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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mm_alu_result = Signal(intbv(0)[32:])
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mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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mm_mem_read = Signal(False)
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mm_mem_read = Signal(False)
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mm_reg_d = Signal(intbv(0)[5:])
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mm_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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mm_reg_write = Signal(False)
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mm_reg_write = Signal(False)
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mm_transfer_size = Signal(transfer_size_type.WORD)
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mm_transfer_size = Signal(transfer_size_type.WORD)
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gprf_dat_a = Signal(intbv(0)[32:])
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gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_b = Signal(intbv(0)[32:])
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gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_d = Signal(intbv(0)[32:])
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gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_flush_id = Signal(False)
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ex_flush_id = Signal(False)
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of_alu_op = Signal(alu_operation.ALU_ADD)
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of_alu_op = Signal(alu_operation.ALU_ADD)
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of_alu_src_a = Signal(src_type_a.REGA)
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of_alu_src_a = Signal(src_type_a.REGA)
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of_alu_src_b = Signal(src_type_b.REGB)
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of_alu_src_b = Signal(src_type_b.REGB)
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of_branch_cond = Signal(branch_condition.NOP)
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of_branch_cond = Signal(branch_condition.NOP)
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of_carry = Signal(carry_type.C_ZERO)
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of_carry = Signal(carry_type.C_ZERO)
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of_carry_keep = Signal(False)
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of_carry_keep = Signal(False)
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of_delay = Signal(False)
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of_delay = Signal(False)
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of_hazard = Signal(False)
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of_hazard = Signal(False)
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of_immediate = Signal(intbv(0)[32:])
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of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_mem_read = Signal(False)
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of_mem_read = Signal(False)
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of_mem_write = Signal(False)
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of_mem_write = Signal(False)
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of_operation = Signal(False)
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of_operation = Signal(False)
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of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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of_reg_a = Signal(intbv(0)[5:])
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of_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_b = Signal(intbv(0)[5:])
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of_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_d = Signal(intbv(0)[5:])
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of_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_write = Signal(False)
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of_reg_write = Signal(False)
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of_transfer_size = Signal(transfer_size_type.WORD)
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of_transfer_size = Signal(transfer_size_type.WORD)
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# Write back stage forwards
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of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_fwd_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_fwd_reg_write = Signal(False)
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ex_alu_result = Signal(intbv(0)[32:])
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ex_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_reg_d = Signal(intbv(0)[5:])
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ex_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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ex_reg_write = Signal(False)
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ex_reg_write = Signal(False)
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ex_branch = Signal(False)
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ex_branch = Signal(False)
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ex_dat_d = Signal(intbv(0)[32:])
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ex_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_flush_id = Signal(False)
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ex_flush_id = Signal(False)
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ex_mem_read = Signal(False)
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ex_mem_read = Signal(False)
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ex_mem_write = Signal(False)
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ex_mem_write = Signal(False)
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ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_transfer_size = Signal(transfer_size_type.WORD)
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ex_transfer_size = Signal(transfer_size_type.WORD)
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kw = dict(
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kw = dict(
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func=ExecuteUnit,
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clock=clock,
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clock=clock,
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reset=reset,
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reset=reset,
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enable=enable,
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enable=enable,
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dmem_data_in=dmem_data_in,
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dmem_data_in=dmem_data_in,
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gprf_dat_a=gprf_dat_a,
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gprf_dat_a=gprf_dat_a,
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Line 472... |
Line 476... |
of_reg_a=of_reg_a,
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of_reg_a=of_reg_a,
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of_reg_b=of_reg_b,
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of_reg_b=of_reg_b,
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of_reg_d=of_reg_d,
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of_reg_d=of_reg_d,
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of_reg_write=of_reg_write,
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of_reg_write=of_reg_write,
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of_transfer_size=of_transfer_size,
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of_transfer_size=of_transfer_size,
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# Write back stage forwards
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of_fwd_mem_result=of_fwd_mem_result,
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of_fwd_reg_d=of_fwd_reg_d,
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of_fwd_reg_write=of_fwd_reg_write,
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# Outputs
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# Outputs
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ex_alu_result=ex_alu_result,
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ex_alu_result=ex_alu_result,
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ex_reg_d=ex_reg_d,
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ex_reg_d=ex_reg_d,
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ex_reg_write=ex_reg_write,
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ex_reg_write=ex_reg_write,
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Line 485... |
Line 493... |
ex_mem_read=ex_mem_read,
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ex_mem_read=ex_mem_read,
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ex_mem_write=ex_mem_write,
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ex_mem_write=ex_mem_write,
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ex_program_counter=ex_program_counter,
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ex_program_counter=ex_program_counter,
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ex_transfer_size=ex_transfer_size,
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ex_transfer_size=ex_transfer_size,
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)
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)
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toVerilog(**kw)
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toVerilog(ExecuteUnit, **kw)
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toVHDL(**kw)
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toVHDL(ExecuteUnit, **kw)
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### EOF ###
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### EOF ###
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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No newline at end of file
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No newline at end of file
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