| Line 6... |
Line 6... |
Top Level of the System Design
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Top Level of the System Design
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:copyright: Copyright (c) 2010 Jian Luo
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:license: LGPL, see LICENSE for details
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:revision: $Id: top.py 3 2010-11-21 07:17:00Z rockee $
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:revision: $Id: top.py 6 2010-11-21 23:18:44Z rockee $
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"""
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"""
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from myhdl import *
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from myhdl import *
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from defines import *
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from defines import *
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from functions import *
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from functions import *
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| Line 40... |
Line 40... |
data_out.next = imem[address[:2]]
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data_out.next = imem[address[:2]]
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return instances()
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return instances()
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def SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
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def SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
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# if __debug__:
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# Ports only for debug
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debug_if_program_counter,
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debug_if_program_counter=0,
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debug_of_alu_op,
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debug_of_alu_src_a,
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debug_of_alu_src_b,
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debug_of_branch_cond,
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debug_of_carry,
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debug_of_carry_keep,
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debug_of_delay,
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debug_of_hazard,
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debug_of_immediate,
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debug_of_instruction,
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debug_of_mem_read,
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debug_of_mem_write,
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debug_of_operation,
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debug_of_program_counter,
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debug_of_reg_a,
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debug_of_reg_b,
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debug_of_reg_d,
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debug_of_reg_write,
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debug_of_transfer_size,
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debug_of_fwd_mem_result,
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debug_of_fwd_reg_d,
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debug_of_fwd_reg_write,
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debug_gprf_dat_a,
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debug_gprf_dat_b,
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debug_gprf_dat_d,
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debug_ex_alu_result,
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debug_ex_reg_d,
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debug_ex_reg_write,
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debug_ex_branch,
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debug_ex_dat_d,
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debug_ex_flush_id,
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debug_ex_mem_read,
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debug_ex_mem_write,
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debug_ex_program_counter,
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debug_ex_transfer_size,
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debug_ex_dat_a,
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debug_of_alu_op=0,
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debug_ex_dat_b,
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debug_of_alu_src_a=0,
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debug_ex_instruction,
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debug_of_alu_src_b=0,
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debug_ex_reg_a,
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debug_of_branch_cond=0,
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debug_ex_reg_b,
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debug_of_carry=0,
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debug_of_carry_keep=0,
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debug_of_delay=0,
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debug_of_hazard=0,
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debug_of_immediate=0,
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debug_of_instruction=0,
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debug_of_mem_read=0,
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debug_of_mem_write=0,
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debug_of_operation=0,
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debug_of_program_counter=0,
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debug_of_reg_a=0,
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debug_of_reg_b=0,
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debug_of_reg_d=0,
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debug_of_reg_write=0,
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debug_of_transfer_size=0,
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debug_of_fwd_mem_result=0,
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debug_of_fwd_reg_d=0,
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debug_of_fwd_reg_write=0,
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debug_gprf_dat_a=0,
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debug_gprf_dat_b=0,
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debug_gprf_dat_d=0,
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debug_ex_alu_result=0,
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debug_ex_reg_d=0,
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debug_ex_reg_write=0,
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debug_ex_branch=0,
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debug_ex_dat_d=0,
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debug_ex_flush_id=0,
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debug_ex_mem_read=0,
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debug_ex_mem_write=0,
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debug_ex_program_counter=0,
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debug_ex_transfer_size=0,
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debug_ex_dat_a=0,
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debug_ex_dat_b=0,
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debug_ex_instruction=0,
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debug_ex_reg_a=0,
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debug_ex_reg_b=0,
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debug_mm_alu_result=0,
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debug_mm_mem_read=0,
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debug_mm_reg_d=0,
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debug_mm_reg_write=0,
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debug_mm_transfer_size=0,
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debug_dmem_ena_in=0,
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debug_dmem_data_in=0,
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debug_dmem_data_out=0,
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debug_dmem_sel_out=0,
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debug_dmem_we_out=0,
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debug_dmem_addr_out=0,
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debug_dmem_ena_out=0,
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debug_dmem_ena=0,
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debug_imem_data_in=0,
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debug_imem_data_out=0,
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debug_imem_sel_out=0,
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debug_imem_we_out=0,
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debug_imem_addr_out=0,
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debug_imem_ena=0,
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debug_imem_ena_out=0,
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debug_mm_alu_result,
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size=4, DEBUG=True):
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debug_mm_mem_read,
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debug_mm_reg_d,
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debug_mm_reg_write,
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debug_mm_transfer_size,
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debug_dmem_ena_in,
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debug_dmem_data_in,
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debug_dmem_data_out,
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debug_dmem_sel_out,
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debug_dmem_we_out,
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debug_dmem_addr_out,
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debug_dmem_ena_out,
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debug_dmem_ena,
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debug_imem_data_in,
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debug_imem_data_out,
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debug_imem_sel_out,
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debug_imem_we_out,
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debug_imem_addr_out,
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debug_imem_ena,
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debug_imem_ena_out,
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size=4):
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rx_data = Signal(intbv(0)[32:])
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rx_data = Signal(intbv(0)[32:])
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rx_avail = Signal(False)
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rx_avail = Signal(False)
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rx_error = Signal(False)
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rx_error = Signal(False)
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read_en = Signal(False)
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read_en = Signal(False)
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tx_data = Signal(intbv(0)[32:])
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tx_data = Signal(intbv(0)[32:])
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| Line 182... |
Line 182... |
dmem_ena_out=dmem_ena_out,
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dmem_ena_out=dmem_ena_out,
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imem_data_in=imem_data_in,
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imem_data_in=imem_data_in,
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imem_addr_out=imem_addr_out,
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imem_addr_out=imem_addr_out,
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imem_ena_out=imem_ena_out,
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imem_ena_out=imem_ena_out,
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# if __debug__:
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# Ports only for debug
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debug_if_program_counter=debug_if_program_counter,
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debug_if_program_counter=debug_if_program_counter,
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debug_of_alu_op=debug_of_alu_op,
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debug_of_alu_op=debug_of_alu_op,
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debug_of_alu_src_a=debug_of_alu_src_a,
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debug_of_alu_src_a=debug_of_alu_src_a,
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debug_of_alu_src_b=debug_of_alu_src_b,
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debug_of_alu_src_b=debug_of_alu_src_b,
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| Line 236... |
Line 236... |
debug_mm_alu_result=debug_mm_alu_result,
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debug_mm_alu_result=debug_mm_alu_result,
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debug_mm_mem_read=debug_mm_mem_read,
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debug_mm_mem_read=debug_mm_mem_read,
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debug_mm_reg_d=debug_mm_reg_d,
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debug_mm_reg_d=debug_mm_reg_d,
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debug_mm_reg_write=debug_mm_reg_write,
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debug_mm_reg_write=debug_mm_reg_write,
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debug_mm_transfer_size=debug_mm_transfer_size,
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debug_mm_transfer_size=debug_mm_transfer_size,
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DEBUG=DEBUG,
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)
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)
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uart = UART(rx_data, rx_avail, rx_error, read_en,
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uart = UART(rx_data, rx_avail, rx_error, read_en,
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tx_data, tx_busy, write_en,
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tx_data, tx_busy, write_en,
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uart_rxd, uart_txd, reset, clock,
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uart_rxd, uart_txd, reset, clock,
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| Line 258... |
Line 260... |
else:
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else:
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dmem_sel.next = 0
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dmem_sel.next = 0
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tx_data.next = dmem_data_out
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tx_data.next = dmem_data_out
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if dmem_addr_out < 2**size:
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if dmem_addr_out < 2**size:
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dmem_ena.next = dmem_ena_out
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dmem_ena.next = dmem_ena_out
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#dmem_ena_in.next = True
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write_en.next = False
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write_en.next = False
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elif dmem_we_out and dmem_addr_out[28:] >= 0xfffffb0:
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elif dmem_we_out and dmem_addr_out[28:] >= 0xfffffc0:
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dmem_ena.next = False
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dmem_ena.next = False
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#dmem_ena_in.next = not tx_busy
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dmem_ena_in.next = not tx_busy
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write_en.next = True
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write_en.next = True
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else:
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else:
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write_en.next = False
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write_en.next = False
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dmem_ena.next = False
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dmem_ena.next = False
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#dmem_ena_in.next = True
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#leds.next = concat(led_reg[4:], led_low[4:])
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#leds.next = concat(led_reg[4:], led_low[4:])
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leds.next = led_reg[8:]
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leds.next = led_reg[8:]
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count = Signal(intbv(0)[20:])
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count = Signal(intbv(0)[20:])
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| Line 295... |
Line 295... |
uart_rxd.next = rxd_line
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uart_rxd.next = rxd_line
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txd_line2.next = uart_txd2
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txd_line2.next = uart_txd2
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uart_rxd2.next = rxd_line2
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uart_rxd2.next = rxd_line2
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read_en.next = False
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read_en.next = False
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count.next = (count+1)%(2**20)
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count.next = (count+1)%(2**20)
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if count == 0:
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#if count == 0:
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led_low.next = concat(led_low[31:], led_low[31])
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#led_low.next = concat(led_low[31:], led_low[31])
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#if write_en and not tx_busy:
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#if write_en and not tx_busy:
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#led_reg.next = concat(led_reg[31:], led_reg[31])
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#led_reg.next = concat(led_reg[31:], led_reg[31])
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#if dmem_we_out and dmem_addr_out[28:] == 0xFFFFFB0:
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if dmem_we_out and dmem_addr_out[28:] == 0xFFFFFB0:
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#led_reg.next = dmem_data_out
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led_reg.next = dmem_data_out
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#else:
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else:
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#led_reg.next = led_reg
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led_reg.next = led_reg
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#led_reg.next = concat(dmem_ena_in, dmem_we_out, dmem_ena_out,
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#led_reg.next = concat(dmem_ena_in, dmem_we_out, dmem_ena_out,
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#write_en,)
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#write_en,)
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if imem_addr_out == 0x244:
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#if imem_addr_out == 0x244:
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led_reg.next = 0xff
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#led_reg.next = 0xff
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@always_comb
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@always_comb
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def debug_output():
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def debug_output():
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debug_dmem_ena_in.next = dmem_ena_in
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debug_dmem_ena_in.next = dmem_ena_in
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| Line 329... |
Line 329... |
debug_imem_we_out.next = imem_we_out
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debug_imem_we_out.next = imem_we_out
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debug_imem_addr_out.next = imem_addr_out
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debug_imem_addr_out.next = imem_addr_out
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debug_imem_ena.next = imem_ena
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debug_imem_ena.next = imem_ena
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debug_imem_ena_out.next = imem_ena_out
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debug_imem_ena_out.next = imem_ena_out
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return instances()
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if DEBUG:
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return imem, dmem, core, uart, uart2, glue, run, debug_output
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return imem, dmem, core, uart, uart2, glue, run
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import sys
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import sys
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from numpy import log2
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from numpy import log2
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def TopBench():
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def TopBench():
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| Line 422... |
Line 425... |
debug_imem_ena = Signal(True)
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debug_imem_ena = Signal(True)
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debug_imem_ena_out = Signal(False)
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debug_imem_ena_out = Signal(False)
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top = SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
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top = SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
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|
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# if __debug__:
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# Ports only for debug
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debug_if_program_counter,
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debug_if_program_counter,
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|
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debug_of_alu_op,
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debug_of_alu_op,
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debug_of_alu_src_a,
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debug_of_alu_src_a,
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debug_of_alu_src_b,
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debug_of_alu_src_b,
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| Line 511... |
Line 514... |
reset.next = False
|
reset.next = False
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yield delay(37)
|
yield delay(37)
|
reset.next = True
|
reset.next = True
|
yield delay(53)
|
yield delay(53)
|
reset.next = False
|
reset.next = False
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for i in range(2000):
|
for i in range(3000):
|
yield clock.negedge
|
yield clock.negedge
|
reset.next = False
|
reset.next = False
|
yield delay(37)
|
yield delay(37)
|
reset.next = True
|
reset.next = True
|
yield delay(53)
|
yield delay(53)
|
reset.next = False
|
reset.next = False
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for i in range(2000):
|
for i in range(3000):
|
yield clock.negedge
|
yield clock.negedge
|
|
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raise StopSimulation
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raise StopSimulation
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|
|
@instance
|
@instance
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| Line 537... |
Line 540... |
#if debug_ex_program_counter == 0x244:
|
#if debug_ex_program_counter == 0x244:
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#print 'reach the second xil_print call'
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#print 'reach the second xil_print call'
|
if debug_dmem_addr_out == 0xffffffc0:
|
if debug_dmem_addr_out == 0xffffffc0:
|
#if debug_dmem_sel_out == 0b1000:
|
#if debug_dmem_sel_out == 0b1000:
|
if debug_dmem_we_out:
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if debug_dmem_we_out:
|
#sys.stdout.write(chr(int(debug_dmem_data_out[8:])))
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sys.stdout.write(chr(int(debug_dmem_data_out[8:])))
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#sys.stdout.flush()
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sys.stdout.flush()
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print int(debug_dmem_data_out[8:])
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#print int(debug_dmem_data_out[8:])
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#print 'output: %d' % debug_dmem_data_out[8:]
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#print 'output: %d' % debug_dmem_data_out[8:]
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| Line 599... |
Line 602... |
|
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return instances()
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return instances()
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|
|
if __name__ == '__main__':
|
if __name__ == '__main__':
|
if 1:
|
if 0:
|
#tb = traceSignals(TopBench)
|
tb = traceSignals(TopBench)
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#Simulation(tb).run()
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Simulation(tb).run()
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conversion.verify.simulator = 'icarus'
|
#conversion.verify.simulator = 'icarus'
|
conversion.verify(TopBench)
|
#conversion.verify(TopBench)
|
else:
|
else:
|
prepare()
|
prepare()
|
txd_line = Signal(False)
|
txd_line = Signal(False)
|
rxd_line = Signal(False)
|
rxd_line = Signal(False)
|
txd_line2 = Signal(False)
|
txd_line2 = Signal(False)
|
| Line 616... |
Line 619... |
reset = Signal(False)
|
reset = Signal(False)
|
clock = Signal(False)
|
clock = Signal(False)
|
size = int(log2(int(sys.argv[1]))) if len(sys.argv) > 1 else 4
|
size = int(log2(int(sys.argv[1]))) if len(sys.argv) > 1 else 4
|
print 'size=%s' % size
|
print 'size=%s' % size
|
#toVHDL(uart_test_top, txd_line, rxd_line, leds, reset, clock)
|
#toVHDL(uart_test_top, txd_line, rxd_line, leds, reset, clock)
|
toVerilog(SysTop, txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock, size=size)
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toVerilog(SysTop, txd_line, rxd_line, txd_line2, rxd_line2, leds, reset,
|
|
clock, size=size, DEBUG=False)
|
|
|
|
|
|
|
### EOF ###
|
### EOF ###
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
|
|
