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[/] [nand_controller/] [trunk/] [VHDL/] [nand_master.vhd] - Diff between revs 10 and 12
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| Rev 10 |
Rev 12 |
| Line 24... |
Line 24... |
entity nand_master is
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entity nand_master is
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port
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port
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(
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(
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-- System clock
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-- System clock
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clk : in std_logic;
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clk : in std_logic;
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enable : in std_logic;
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-- NAND chip control hardware interface. These signals should be bound to physical pins.
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-- NAND chip control hardware interface. These signals should be bound to physical pins.
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nand_cle : out std_logic := '0';
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nand_cle : out std_logic := '0';
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nand_ale : out std_logic := '0';
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nand_ale : out std_logic := '0';
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nand_nwe : out std_logic := '1';
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nand_nwe : out std_logic := '1';
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nand_nwp : out std_logic := '0';
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nand_nwp : out std_logic := '0';
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| Line 278... |
Line 279... |
state <= M_RESET;
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state <= M_RESET;
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-- elsif(activate = '1')then
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-- elsif(activate = '1')then
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-- state <= state_switch(to_integer(unsigned(cmd_in)));
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-- state <= state_switch(to_integer(unsigned(cmd_in)));
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elsif(rising_edge(clk))then
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elsif(rising_edge(clk) and enable = '0')then
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case state is
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case state is
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-- RESET state. Speaks for itself
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-- RESET state. Speaks for itself
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when M_RESET =>
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when M_RESET =>
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state <= M_IDLE;
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state <= M_IDLE;
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substate <= MS_BEGIN;
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substate <= MS_BEGIN;
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| Line 310... |
Line 311... |
-- Reset the NAND chip
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-- Reset the NAND chip
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when M_NAND_RESET =>
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when M_NAND_RESET =>
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cle_data_in <= x"00ff";
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cle_data_in <= x"00ff";
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state <= M_WAIT;
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state <= M_WAIT;
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n_state <= M_IDLE;
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n_state <= M_IDLE;
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delay <= t_wb + 8;
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-- Read the status register of the controller
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-- Read the status register of the controller
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when MI_GET_STATUS =>
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when MI_GET_STATUS =>
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data_out <= status;
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data_out <= status;
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state <= M_IDLE;
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state <= M_IDLE;
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| Line 767... |
Line 769... |
end if;
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end if;
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end if;
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end if;
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-- Wait for latch and IO modules to become ready as well as for NAND's R/B# to be '1'
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-- Wait for latch and IO modules to become ready as well as for NAND's R/B# to be '1'
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when M_WAIT =>
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when M_WAIT =>
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if('0' = (cle_busy or ale_busy or io_rd_busy or io_wr_busy or (not nand_rnb)))then
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if(delay > 1)then
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delay <= delay - 1;
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elsif('0' = (cle_busy or ale_busy or io_rd_busy or io_wr_busy or (not nand_rnb)))then
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state <= n_state;
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state <= n_state;
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end if;
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end if;
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-- Simple delay mechanism
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-- Simple delay mechanism
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when M_DELAY =>
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when M_DELAY =>
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