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| 0x305 | **Machine trap-handler base address** | `mtvec`
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| 0x305 | **Machine trap-handler base address** | `mtvec`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _UNDEFINED_
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3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
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3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
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traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
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traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
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source. The lowest two bits of this register are always zero and cannot be modified (= address mode only).
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source. The lowest two bits of this register are always zero and cannot be modified (= address mode only).
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Hence, the trap handler's base address has to be aligned to a 4-byte boundary.
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|=======================
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|=======================
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.Machine trap-handler base address
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.Machine trap-handler base address
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|=======================
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|=======================
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| 0x343 | **Machine bad address or instruction** | `mtval`
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| 0x343 | **Machine bad address or instruction** | `mtval`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _UNDEFINED_
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3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
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3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
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the faulting address (for misaligned/faulting load/stores/fetch) or the faulting instruction itself (for illegal
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the faulting address (for misaligned/faulting load/store/fetch) or the faulting (decompressed) instruction word itself (for illegal
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instructions). For interrupts the CSR is set to zero.
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instructions). For all other exceptions (including interrupts) the CSR is set to zero.
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|=======================
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|=======================
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.Machine bad address or instruction register
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.Machine bad address or instruction register
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|=======================
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|=======================
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| Trap cause | `mtval` content
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| Trap cause | `mtval` content
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| misaligned instruction fetch address or instruction fetch access fault | address of faulting instruction fetch
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| misaligned instruction fetch address or instruction fetch access fault | address of faulting instruction fetch
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| breakpoint | program counter (= address) of faulting instruction itself
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| misaligned load address, load access fault, misaligned store address or store access fault | program counter (= address) of faulting instruction
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| misaligned load address, load access fault, misaligned store address or store access fault | program counter (= address) of faulting instruction itself
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| illegal instruction | actual instruction word of faulting instruction (decoded 32-bit instruction word if caused by a compressed instruction)
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| illegal instruction | actual instruction word of faulting instruction
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| anything else including interrupts | _0x00000000_ (always zero)
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| anything else including interrupts | _0x00000000_ (always zero)
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|=======================
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|=======================
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|
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[IMPORTAN]
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[IMPORTANT]
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The NEORV32 `mtval` CSR is read-only. However, a write access will _NOT_ raise an illegal instruction exception.
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The NEORV32 `mtval` CSR is read-only. However, a write access will _NOT_ raise an illegal instruction exception.
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[NOTE]
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In case an invalid compressed instruction raised an illegal instruction exception, `mtval` will show the
|
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according de-compressed instruction word. To get the "real" 16-bit instruction that caused the exception
|
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perform a memory load using the address stored in <<_mepc>>.
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:sectnums!:
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:sectnums!:
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===== **`mip`**
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===== **`mip`**
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