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The TRNG is based on the _neoTRNG_, which is a "spin-off project" of the
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The TRNG is based on the _neoTRNG_, which is a "spin-off project" of the
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NEORV32 processor. The TRNG uses the default neoTRNG configuration, which showed very good results in the
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NEORV32 processor. The TRNG uses the default neoTRNG configuration, which showed very good results in the
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`dieharder` battery of random number tests. More detailed information about the neoTRNG, it's architecture and a
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`dieharder` battery of random number tests. More detailed information about the neoTRNG, it's architecture and a
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detailed evaluation of the random number quality can be found it it's repository: https://github.com/stnolting/neoTRNG
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detailed evaluation of the random number quality can be found it it's repository: https://github.com/stnolting/neoTRNG
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.Platform Independent Architecture
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[NOTE]
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[NOTE]
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The TRNG features a platform independent architecture without FPGA-specific primitives, macros or
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The TRNG features a platform independent architecture without FPGA-specific primitives, macros or
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attributes so it can be synthesized for _any_ FPGA.
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attributes so it can be synthesized for _any_ FPGA.
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.Inferring Latches
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[NOTE]
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The synthesis tool might emit a warning like _"inferring latches for ... neorv32_trng ..."_. This is no problem
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as this is what we actually want (the TRNG is based on latches).
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**Using the TRNG**
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**Using the TRNG**
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The TRNG features a single register for status and data access. When the _TRNG_CTRL_EN_ control register (`CTRL`)
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The TRNG features a single register for status and data access. When the _TRNG_CTRL_EN_ control register (`CTRL`)
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bit is set, the TRNG is enabled and starts operation. As soon as the _TRNG_CTRL_VALID_ bit is set, the currently
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bit is set, the TRNG is enabled and starts operation. As soon as the _TRNG_CTRL_VALID_ bit is set, the currently
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sampled 8-bit random data byte can be obtained from the lowest 8 bits of the `CTRL` register
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sampled 8-bit random data byte can be obtained from the lowest 8 bits of the `CTRL` register
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(_TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_LSB_). These bits always keep the latest valid data obtained from the TRNG
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(_TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_LSB_). These bits always keep the latest valid data obtained from the TRNG
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entropy source. The _TRNG_CTRL_VALID_ bit is automatically cleared when reading the control register.
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entropy source. The _TRNG_CTRL_VALID_ bit is automatically cleared when reading the control register.
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.TRNG Reset
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[NOTE]
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[NOTE]
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The TRNG core does not provide a dedicated reset. In order to ensure correct operations, the TRNG should be
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The TRNG core does not provide a dedicated reset. In order to ensure correct operations, the TRNG should be
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disabled (=reset) by clearing the _TRNG_CTRL_EN_ and waiting some milliseconds before re-enabling it.
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disabled (=reset) by clearing the _TRNG_CTRL_EN_ and waiting some milliseconds before re-enabling it.
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