URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [docs/] [legal.adoc] - Diff between revs 72 and 74

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`ARISING IN ANY WAY OUT OF`	`ARISING IN ANY WAY OUT OF`


`==========================`	`==========================`
`The NEORV32 RISC-V Processor +`	`The NEORV32 RISC-V Processor +`
`Copyright (c) 2022, by Dipl.-Ing. Stephan Nolting. All rights reserved. +`	`By Dipl.-Ing. Stephan Nolting +`
`HQ: https://github.com/stnolting/neorv32 +`
`Contact: stnolting@gmail.com +`	`Contact: stnolting@gmail.com +`
`_made in Hanover, Germany_`	`HQ: https://github.com/stnolting/neorv32`
`==========================`	`==========================`


`// ####################################################################################################################`	`// ####################################################################################################################`
`:sectnums!:`	`:sectnums!:`
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`who helped improving this project! ❤️**`	`who helped improving this project! ❤️**`

`https://riscv.org[RISC-V] - instruction sets want to be free!`	`https://riscv.org[RISC-V] - instruction sets want to be free!`

`Continuous integration provided by https://github.com/features/actions[GitHub Actions] and powered by https://github.com/ghdl/ghdl[GHDL].`	`Continuous integration provided by https://github.com/features/actions[GitHub Actions] and powered by https://github.com/ghdl/ghdl[GHDL].`


`=== Impressum (Imprint)`

See https://github.com/stnolting/neorv32/blob/main/docs/impressum.md[`docs/impressum.md`].