| Line 113... |
Line 113... |
constant pmp_cfg_r_c : natural := 0; -- read permit
|
constant pmp_cfg_r_c : natural := 0; -- read permit
|
constant pmp_cfg_w_c : natural := 1; -- write permit
|
constant pmp_cfg_w_c : natural := 1; -- write permit
|
constant pmp_cfg_x_c : natural := 2; -- execute permit
|
constant pmp_cfg_x_c : natural := 2; -- execute permit
|
constant pmp_cfg_al_c : natural := 3; -- mode bit low
|
constant pmp_cfg_al_c : natural := 3; -- mode bit low
|
constant pmp_cfg_ah_c : natural := 4; -- mode bit high
|
constant pmp_cfg_ah_c : natural := 4; -- mode bit high
|
--
|
|
constant pmp_cfg_l_c : natural := 7; -- locked entry
|
constant pmp_cfg_l_c : natural := 7; -- locked entry
|
|
|
-- PMP minimal granularity --
|
-- PMP minimal granularity --
|
constant pmp_lsb_c : natural := index_size_f(PMP_MIN_GRANULARITY);
|
constant pmp_lsb_c : natural := index_size_f(PMP_MIN_GRANULARITY);
|
|
|
-- data interface registers --
|
-- data memory address register --
|
signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0);
|
|
|
-- data access --
|
-- data access --
|
signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
signal rdata_align : std_ulogic_vector(data_width_c-1 downto 0); -- read-data alignment
|
signal rdata_align : std_ulogic_vector(data_width_c-1 downto 0); -- read-data alignment
|
| Line 195... |
Line 194... |
-- Data Interface: Write Data -------------------------------------------------------------
|
-- Data Interface: Write Data -------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_do_reg: process(rstn_i, clk_i)
|
mem_do_reg: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
mdo <= (others => def_rst_val_c);
|
d_bus_wdata <= (others => def_rst_val_c);
|
|
d_bus_ben <= (others => def_rst_val_c);
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
mdo <= wdata_i; -- memory data output register (MDO)
|
-- byte enable and data alignment --
|
end if;
|
|
end if;
|
|
end process mem_do_reg;
|
|
|
|
-- byte enable and output data alignment --
|
|
write_align: process(mar, mdo, ctrl_i)
|
|
begin
|
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
when "00" => -- byte
|
when "00" => -- byte
|
d_bus_wdata(07 downto 00) <= mdo(7 downto 0);
|
d_bus_wdata(07 downto 00) <= wdata_i(7 downto 0);
|
d_bus_wdata(15 downto 08) <= mdo(7 downto 0);
|
d_bus_wdata(15 downto 08) <= wdata_i(7 downto 0);
|
d_bus_wdata(23 downto 16) <= mdo(7 downto 0);
|
d_bus_wdata(23 downto 16) <= wdata_i(7 downto 0);
|
d_bus_wdata(31 downto 24) <= mdo(7 downto 0);
|
d_bus_wdata(31 downto 24) <= wdata_i(7 downto 0);
|
case mar(1 downto 0) is
|
case addr_i(1 downto 0) is
|
when "00" => d_bus_ben <= "0001";
|
when "00" => d_bus_ben <= "0001";
|
when "01" => d_bus_ben <= "0010";
|
when "01" => d_bus_ben <= "0010";
|
when "10" => d_bus_ben <= "0100";
|
when "10" => d_bus_ben <= "0100";
|
when others => d_bus_ben <= "1000";
|
when others => d_bus_ben <= "1000";
|
end case;
|
end case;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
d_bus_wdata(31 downto 16) <= mdo(15 downto 0);
|
d_bus_wdata(31 downto 16) <= wdata_i(15 downto 0);
|
d_bus_wdata(15 downto 00) <= mdo(15 downto 0);
|
d_bus_wdata(15 downto 00) <= wdata_i(15 downto 0);
|
if (mar(1) = '0') then
|
if (addr_i(1) = '0') then
|
d_bus_ben <= "0011"; -- low half-word
|
d_bus_ben <= "0011"; -- low half-word
|
else
|
else
|
d_bus_ben <= "1100"; -- high half-word
|
d_bus_ben <= "1100"; -- high half-word
|
end if;
|
end if;
|
when others => -- word
|
when others => -- word
|
d_bus_wdata <= mdo;
|
d_bus_wdata <= wdata_i;
|
d_bus_ben <= "1111"; -- full word
|
d_bus_ben <= "1111"; -- full word
|
end case;
|
end case;
|
end process write_align;
|
end if;
|
|
end if;
|
|
end process mem_do_reg;
|
|
|
|
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_di_reg: process(rstn_i, clk_i)
|
read_align: process(rstn_i, clk_i)
|
|
variable shifted_data_v : std_ulogic_vector(31 downto 0);
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
mdi <= (others => def_rst_val_c);
|
rdata_align <= (others => def_rst_val_c);
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
|
|
mdi <= d_bus_rdata; -- memory data input register (MDI)
|
|
end if;
|
|
end if;
|
|
end process mem_di_reg;
|
|
|
|
-- input data alignment and sign extension --
|
-- input data alignment and sign extension --
|
read_align: process(mdi, mar, ctrl_i)
|
|
variable shifted_data_v : std_ulogic_vector(31 downto 0);
|
|
begin
|
|
-- align input word --
|
|
case mar(1 downto 0) is
|
|
when "00" => shifted_data_v := mdi(31 downto 00);
|
|
when "01" => shifted_data_v := x"00" & mdi(31 downto 08);
|
|
when "10" => shifted_data_v := x"0000" & mdi(31 downto 16);
|
|
when others => shifted_data_v := x"000000" & mdi(31 downto 24);
|
|
end case;
|
|
-- actual data size and sign-extension --
|
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
|
when "00" => -- byte
|
when "00" => -- byte
|
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and shifted_data_v(7))); -- sign extension
|
case mar(1 downto 0) is
|
rdata_align(07 downto 00) <= shifted_data_v(07 downto 00);
|
when "00" => -- byte 0
|
|
rdata_align(07 downto 00) <= d_bus_rdata(07 downto 00);
|
|
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and d_bus_rdata(07))); -- sign extension
|
|
when "01" => -- byte 1
|
|
rdata_align(07 downto 00) <= d_bus_rdata(15 downto 08);
|
|
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and d_bus_rdata(15))); -- sign extension
|
|
when "10" => -- byte 2
|
|
rdata_align(07 downto 00) <= d_bus_rdata(23 downto 16);
|
|
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and d_bus_rdata(23))); -- sign extension
|
|
when others => -- byte 3
|
|
rdata_align(07 downto 00) <= d_bus_rdata(31 downto 24);
|
|
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and d_bus_rdata(31))); -- sign extension
|
|
end case;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and shifted_data_v(15))); -- sign extension
|
if (mar(1) = '0') then
|
rdata_align(15 downto 00) <= shifted_data_v(15 downto 00); -- high half-word
|
rdata_align(15 downto 00) <= d_bus_rdata(15 downto 00); -- low half-word
|
|
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and d_bus_rdata(15))); -- sign extension
|
|
else
|
|
rdata_align(15 downto 00) <= d_bus_rdata(31 downto 16); -- high half-word
|
|
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and d_bus_rdata(31))); -- sign extension
|
|
end if;
|
when others => -- word
|
when others => -- word
|
rdata_align <= shifted_data_v; -- full word
|
rdata_align <= d_bus_rdata; -- full word
|
end case;
|
end case;
|
|
end if;
|
end process read_align;
|
end process read_align;
|
|
|
-- insert exclusive lock status for SC operations only --
|
-- insert exclusive lock status for SC operations only --
|
rdata_o <= exclusive_lock_status when (CPU_EXTENSION_RISCV_A = true) and (ctrl_i(ctrl_bus_ch_lock_c) = '1') else rdata_align;
|
rdata_o <= exclusive_lock_status when (CPU_EXTENSION_RISCV_A = true) and (ctrl_i(ctrl_bus_ch_lock_c) = '1') else rdata_align;
|
|
|
|
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- Data Interface: Arbiter (controlled by pipeline back-end) ------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- controlled by pipeline BACK-end --
|
|
data_access_arbiter: process(rstn_i, clk_i)
|
data_access_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- data access request --
|
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
else -- in progress, accumulate error
|
else -- in progress, accumulate errors
|
d_arbiter.err_align <= d_arbiter.err_align or d_misaligned;
|
d_arbiter.err_align <= d_arbiter.err_align or d_misaligned;
|
d_arbiter.err_bus <= d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req);
|
d_arbiter.err_bus <= d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req);
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- wait for ACK or TRAP
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- wait for ACK or TRAP
|
-- > do not abort directly when an error has been detected - wait until the trap environment
|
-- > do not abort directly when an error has been detected - wait until the trap environment
|
-- > has started (ctrl_i(ctrl_trap_c)) to make sure the error signals are evaluated BEFORE d_wait_o clears
|
-- > has started (ctrl_i(ctrl_trap_c)) to make sure the error signals are evaluated BEFORE d_wait_o clears
|
| Line 325... |
Line 320... |
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
|
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_rdata <= d_bus_rdata_i;
|
d_bus_rdata <= d_bus_rdata_i;
|
|
|
-- check data access address alignment --
|
-- check data access address alignment --
|
misaligned_d_check: process(mar, ctrl_i)
|
misaligned_d_check: process(rstn_i, clk_i)
|
begin
|
begin
|
|
if (rstn_i = '0') then
|
|
d_misaligned <= def_rst_val_c;
|
|
elsif rising_edge(clk_i) then
|
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
when "00" => -- byte
|
when "00" => d_misaligned <= '0'; -- byte
|
d_misaligned <= '0';
|
when "01" => d_misaligned <= addr_i(0); -- half-word
|
when "01" => -- half-word
|
when others => d_misaligned <= addr_i(1) or addr_i(0); -- word
|
if (mar(0) /= '0') then
|
end case;
|
d_misaligned <= '1';
|
|
else
|
|
d_misaligned <= '0';
|
|
end if;
|
end if;
|
when others => -- word
|
|
if (mar(1 downto 0) /= "00") then
|
|
d_misaligned <= '1';
|
|
else
|
|
d_misaligned <= '0';
|
|
end if;
|
end if;
|
end case;
|
|
end process misaligned_d_check;
|
end process misaligned_d_check;
|
|
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
|
pmp_dbus_buffer: process(rstn_i, clk_i)
|
pmp_dbus_buffer: process(rstn_i, clk_i)
|
begin
|
begin
|
| Line 366... |
Line 356... |
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
exclusive_lock <= '0';
|
exclusive_lock <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (ctrl_i(ctrl_trap_c) = '1') or (ctrl_i(ctrl_bus_de_lock_c) = '1') then -- remove lock if entering a trap or executing a non-load-reservate memory access
|
-- remove lock if entering a trap or executing a non-load-reservate memory access --
|
|
if (ctrl_i(ctrl_trap_c) = '1') or (ctrl_i(ctrl_bus_de_lock_c) = '1') then
|
exclusive_lock <= '0';
|
exclusive_lock <= '0';
|
elsif (ctrl_i(ctrl_bus_lock_c) = '1') then -- set new lock
|
elsif (ctrl_i(ctrl_bus_lock_c) = '1') then -- set new lock
|
exclusive_lock <= '1';
|
exclusive_lock <= '1';
|
end if;
|
end if;
|
else
|
else
|
| Line 389... |
Line 380... |
-- output to memory system --
|
-- output to memory system --
|
i_bus_lock_o <= '0'; -- instruction fetches cannot be locked
|
i_bus_lock_o <= '0'; -- instruction fetches cannot be locked
|
d_bus_lock_o <= exclusive_lock;
|
d_bus_lock_o <= exclusive_lock;
|
|
|
|
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- Instruction Interface: Arbiter (controlled by pipeline front-end) ----------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- controlled by pipeline FRONT-end --
|
|
ifetch_arbiter: process(rstn_i, clk_i)
|
ifetch_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
i_arbiter.rd_req <= '0';
|
i_arbiter.rd_req <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.err_bus <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- instruction fetch request --
|
|
if (i_arbiter.rd_req = '0') then -- idle
|
if (i_arbiter.rd_req = '0') then -- idle
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.err_bus <= '0';
|
else -- in progress, accumulate errors
|
else -- in progress, accumulate errors
|
| Line 450... |
Line 439... |
end process pmp_ibus_buffer;
|
end process pmp_ibus_buffer;
|
|
|
|
|
-- Physical Memory Protection (PMP) -------------------------------------------------------
|
-- Physical Memory Protection (PMP) -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- check access address region --
|
|
|
-- check address region --
|
pmp_check_address: process(pmp_addr_i, fetch_pc_i, mar)
|
pmp_check_address: process(pmp_addr_i, fetch_pc_i, mar)
|
begin
|
begin
|
for i in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
|
for i in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
|
if (i = 0) then -- use ZERO as bottom boundary and current entry as top boundary for first entry
|
if (i = 0) then -- use ZERO as bottom boundary and current entry as top boundary for first entry
|
pmp.i_match(i) <= bool_to_ulogic_f(unsigned(fetch_pc_i(data_width_c-1 downto pmp_lsb_c)) < unsigned(pmp_addr_i(0)(data_width_c-1 downto pmp_lsb_c)));
|
pmp.i_match(i) <= bool_to_ulogic_f(unsigned(fetch_pc_i(data_width_c-1 downto pmp_lsb_c)) < unsigned(pmp_addr_i(0)(data_width_c-1 downto pmp_lsb_c)));
|
| Line 484... |
Line 474... |
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end process pmp_check_permission;
|
end process pmp_check_permission;
|
|
|
-- final PMP access fault signals --
|
-- final PMP access fault signals --
|
if_pmp_fault <= or_reduce_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
if_pmp_fault <= '1' when (or_reduce_f(pmp.if_fault) = '1') and (PMP_NUM_REGIONS > 0) else '0';
|
ld_pmp_fault <= or_reduce_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
ld_pmp_fault <= '1' when (or_reduce_f(pmp.ld_fault) = '1') and (PMP_NUM_REGIONS > 0) else '0';
|
st_pmp_fault <= or_reduce_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
st_pmp_fault <= '1' when (or_reduce_f(pmp.st_fault) = '1') and (PMP_NUM_REGIONS > 0) else '0';
|
|
|
|
|
end neorv32_cpu_bus_rtl;
|
end neorv32_cpu_bus_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
