| Line 150... |
Line 150... |
state : fetch_engine_state_t;
|
state : fetch_engine_state_t;
|
state_nxt : fetch_engine_state_t;
|
state_nxt : fetch_engine_state_t;
|
state_prev : fetch_engine_state_t;
|
state_prev : fetch_engine_state_t;
|
restart : std_ulogic;
|
restart : std_ulogic;
|
restart_nxt : std_ulogic;
|
restart_nxt : std_ulogic;
|
|
align : std_ulogic;
|
|
align_nxt : std_ulogic;
|
pc : std_ulogic_vector(data_width_c-1 downto 0);
|
pc : std_ulogic_vector(data_width_c-1 downto 0);
|
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
|
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
|
reset : std_ulogic;
|
reset : std_ulogic;
|
bus_ir : std_ulogic;
|
bus_if : std_ulogic;
|
end record;
|
end record;
|
signal fetch_engine : fetch_engine_t;
|
signal fetch_engine : fetch_engine_t;
|
|
|
-- instruction prefetch buffer (FIFO) interface --
|
-- instruction prefetch buffer (FIFO) interface --
|
|
type ipb_data_t is array (0 to 1) of std_ulogic_vector((2+16)-1 downto 0); -- status (bus_error, align_error) + 16-bit instruction
|
type ipb_t is record
|
type ipb_t is record
|
wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data
|
wdata : ipb_data_t;
|
we : std_ulogic; -- trigger write
|
we : std_ulogic_vector(1 downto 0); -- trigger write
|
free : std_ulogic; -- free entry available?
|
free : std_ulogic_vector(1 downto 0); -- free entry available?
|
clear : std_ulogic; -- clear all entries
|
rdata : ipb_data_t;
|
--
|
re : std_ulogic_vector(1 downto 0); -- read enable
|
rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data
|
avail : std_ulogic_vector(1 downto 0); -- data available?
|
re : std_ulogic; -- read enable
|
|
avail : std_ulogic; -- data available?
|
|
end record;
|
end record;
|
signal ipb : ipb_t;
|
signal ipb : ipb_t;
|
|
|
-- pre-decoder --
|
|
signal ci_instr16 : std_ulogic_vector(15 downto 0);
|
|
signal ci_instr32 : std_ulogic_vector(31 downto 0);
|
|
signal ci_illegal : std_ulogic;
|
|
|
|
-- instruction issue engine --
|
-- instruction issue engine --
|
type issue_engine_t is record
|
type issue_engine_t is record
|
realign : std_ulogic;
|
|
realign_nxt : std_ulogic;
|
|
align : std_ulogic;
|
align : std_ulogic;
|
align_nxt : std_ulogic;
|
align_set : std_ulogic;
|
buf : std_ulogic_vector(2+15 downto 0);
|
align_clr : std_ulogic;
|
buf_nxt : std_ulogic_vector(2+15 downto 0);
|
ci_i16 : std_ulogic_vector(15 downto 0);
|
|
ci_i32 : std_ulogic_vector(31 downto 0);
|
|
ci_ill : std_ulogic;
|
|
data : std_ulogic_vector((4+32)-1 downto 0); -- 4-bit status + 32-bit instruction
|
|
valid : std_ulogic_vector(1 downto 0); -- data word is valid when != 0
|
end record;
|
end record;
|
signal issue_engine : issue_engine_t;
|
signal issue_engine : issue_engine_t;
|
|
|
-- instruction issue interface --
|
|
type cmd_issue_t is record
|
|
data : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
|
|
valid : std_ulogic; -- data word is valid when set
|
|
end record;
|
|
signal cmd_issue : cmd_issue_t;
|
|
|
|
-- instruction decoding helper logic --
|
-- instruction decoding helper logic --
|
type decode_aux_t is record
|
type decode_aux_t is record
|
is_a_lr : std_ulogic;
|
is_a_lr : std_ulogic;
|
is_a_sc : std_ulogic;
|
is_a_sc : std_ulogic;
|
is_f_op : std_ulogic;
|
is_f_op : std_ulogic;
|
| Line 209... |
Line 200... |
end record;
|
end record;
|
signal decode_aux : decode_aux_t;
|
signal decode_aux : decode_aux_t;
|
|
|
-- instruction execution engine --
|
-- instruction execution engine --
|
type execute_engine_state_t is (DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT,
|
type execute_engine_state_t is (DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT,
|
BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
|
BRANCH, BRANCHED, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYSTEM);
|
type execute_engine_t is record
|
type execute_engine_t is record
|
state : execute_engine_state_t;
|
state : execute_engine_state_t;
|
state_nxt : execute_engine_state_t;
|
state_nxt : execute_engine_state_t;
|
state_prev : execute_engine_state_t;
|
state_prev : execute_engine_state_t;
|
--
|
--
|
| Line 278... |
Line 269... |
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(data_width_c-1 downto 0);
|
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(data_width_c-1 downto 0);
|
type csr_t is record
|
type csr_t is record
|
addr : std_ulogic_vector(11 downto 0); -- csr address
|
addr : std_ulogic_vector(11 downto 0); -- csr address
|
we : std_ulogic; -- csr write enable
|
we : std_ulogic; -- csr write enable
|
we_nxt : std_ulogic;
|
we_nxt : std_ulogic;
|
|
re : std_ulogic; -- csr read enable
|
|
re_nxt : std_ulogic;
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
--
|
--
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
|
| Line 375... |
Line 368... |
-- (hpm) counter events --
|
-- (hpm) counter events --
|
signal cnt_event : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
signal cnt_event : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
|
signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
|
|
|
-- illegal instruction check --
|
-- illegal instruction check --
|
signal illegal_opcode_lsbs : std_ulogic; -- opcode != rv32
|
signal illegal_cmd : std_ulogic;
|
signal illegal_instruction : std_ulogic;
|
signal illegal_reg : std_ulogic; -- illegal register (>x15) - E-extension
|
signal illegal_register : std_ulogic; -- illegal register (>x15) - E-extension
|
|
signal illegal_compressed : std_ulogic; -- illegal compressed instruction - C-extension
|
|
|
|
-- access (privilege) check --
|
-- access (privilege) check --
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
|
|
-- hardware trigger module --
|
-- hardware trigger module --
|
| Line 400... |
Line 391... |
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
fetch_engine.state <= IFETCH_REQUEST;
|
fetch_engine.state <= IFETCH_REQUEST;
|
fetch_engine.state_prev <= IFETCH_REQUEST;
|
fetch_engine.state_prev <= IFETCH_REQUEST;
|
fetch_engine.restart <= '1';
|
fetch_engine.restart <= '1';
|
|
fetch_engine.align <= '0'; -- always start at aligned address after reset
|
fetch_engine.pc <= (others => def_rst_val_c);
|
fetch_engine.pc <= (others => def_rst_val_c);
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
fetch_engine.state <= fetch_engine.state_nxt;
|
fetch_engine.state <= fetch_engine.state_nxt;
|
fetch_engine.state_prev <= fetch_engine.state;
|
fetch_engine.state_prev <= fetch_engine.state;
|
fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset;
|
fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset;
|
|
fetch_engine.align <= fetch_engine.align_nxt and bool_to_ulogic_f(CPU_EXTENSION_RISCV_C);
|
fetch_engine.pc <= fetch_engine.pc_nxt;
|
fetch_engine.pc <= fetch_engine.pc_nxt;
|
end if;
|
end if;
|
end process fetch_engine_fsm_sync;
|
end process fetch_engine_fsm_sync;
|
|
|
-- PC output --
|
-- PC output --
|
| Line 418... |
Line 411... |
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
|
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
fetch_engine.bus_ir <= '0';
|
fetch_engine.bus_if <= '0';
|
fetch_engine.state_nxt <= fetch_engine.state;
|
fetch_engine.state_nxt <= fetch_engine.state;
|
fetch_engine.pc_nxt <= fetch_engine.pc;
|
fetch_engine.pc_nxt <= fetch_engine.pc;
|
fetch_engine.restart_nxt <= fetch_engine.restart;
|
fetch_engine.restart_nxt <= fetch_engine.restart;
|
|
fetch_engine.align_nxt <= fetch_engine.align;
|
|
|
-- instruction prefetch buffer defaults --
|
-- instruction prefetch buffer defaults --
|
ipb.we <= '0';
|
ipb.we <= "00";
|
ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
|
ipb.wdata(0) <= be_instr_i & ma_instr_i & instr_i(15 downto 00);
|
|
ipb.wdata(1) <= be_instr_i & ma_instr_i & instr_i(31 downto 16);
|
|
|
-- state machine --
|
-- state machine --
|
if (fetch_engine.state = IFETCH_REQUEST) then -- IFETCH_REQUEST: request new 32-bit-aligned instruction word
|
if (fetch_engine.state = IFETCH_REQUEST) then -- REQUEST: request new 32-bit-aligned instruction word
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (fetch_engine.restart = '1') then -- reset request
|
if (fetch_engine.restart = '1') then -- reset request
|
fetch_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
fetch_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
elsif (ipb.free = '1') then -- free entry in buffer
|
fetch_engine.align_nxt <= execute_engine.pc(1);
|
fetch_engine.bus_ir <= '1'; -- instruction fetch request
|
elsif (ipb.free = "11") then -- free entries in both buffers
|
|
fetch_engine.bus_if <= '1'; -- instruction fetch request
|
fetch_engine.state_nxt <= IFETCH_ISSUE;
|
fetch_engine.state_nxt <= IFETCH_ISSUE;
|
end if;
|
end if;
|
fetch_engine.restart_nxt <= '0';
|
fetch_engine.restart_nxt <= '0'; -- restart done
|
|
|
else -- IFETCH_ISSUE: store instruction data to prefetch buffer
|
else -- ISSUE: store instruction data to prefetch buffer
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
|
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
|
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
|
fetch_engine.align_nxt <= '0';
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
|
if (fetch_engine.restart = '0') then -- write to IPB if not being reset
|
|
ipb.we(0) <= not fetch_engine.align; -- not start at unaligned address
|
|
ipb.we(1) <= '1';
|
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process fetch_engine_fsm_comb;
|
end process fetch_engine_fsm_comb;
|
|
|
-- clear instruction prefetch buffer while being reset --
|
|
ipb.clear <= fetch_engine.restart or fetch_engine.reset;
|
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Prefetch Buffer
|
-- Instruction Prefetch Buffer
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
instr_prefetch_buffer: neorv32_fifo
|
prefetch_buffer:
|
|
for i in 0 to 1 generate -- high half-word and low half-word
|
|
prefetch_buffer_inst: neorv32_fifo
|
generic map (
|
generic map (
|
FIFO_DEPTH => CPU_IPB_ENTRIES, -- number of fifo entries; has to be a power of two; min 1
|
FIFO_DEPTH => CPU_IPB_ENTRIES, -- number of fifo entries; has to be a power of two; min 1
|
FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo
|
FIFO_WIDTH => ipb.wdata(i)'length, -- size of data elements in fifo
|
FIFO_RSYNC => false, -- we NEED to read data asynchronously
|
FIFO_RSYNC => false, -- we NEED to read data asynchronously
|
FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
|
FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
|
)
|
)
|
port map (
|
port map (
|
-- control --
|
-- control --
|
clk_i => clk_i, -- clock, rising edge
|
clk_i => clk_i, -- clock, rising edge
|
rstn_i => '1', -- async reset, low-active
|
rstn_i => '1', -- async reset, low-active
|
clear_i => ipb.clear, -- sync reset, high-active
|
clear_i => fetch_engine.restart, -- sync reset, high-active
|
level_o => open,
|
level_o => open,
|
half_o => open,
|
half_o => open,
|
-- write port --
|
-- write port --
|
wdata_i => ipb.wdata, -- write data
|
wdata_i => ipb.wdata(i), -- write data
|
we_i => ipb.we, -- write enable
|
we_i => ipb.we(i), -- write enable
|
free_o => ipb.free, -- at least one entry is free when set
|
free_o => ipb.free(i), -- at least one entry is free when set
|
-- read port --
|
-- read port --
|
re_i => ipb.re, -- read enable
|
re_i => ipb.re(i), -- read enable
|
rdata_o => ipb.rdata, -- read data
|
rdata_o => ipb.rdata(i), -- read data
|
avail_o => ipb.avail -- data available when set
|
avail_o => ipb.avail(i) -- data available when set
|
);
|
);
|
|
end generate;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)
|
-- Instruction Issue (decompress 16-bit instructions and assemble 32-bit instruction word)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Issue Engine FSM Sync ------------------------------------------------------------------
|
-- Issue Engine FSM Sync ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then -- always start aligned after reset
|
if (rstn_i = '0') then
|
issue_engine.align <= '0';
|
issue_engine.align <= '0'; -- always start aligned after reset
|
issue_engine.realign <= '0';
|
|
issue_engine.buf <= (others => def_rst_val_c);
|
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (ipb.clear = '1') then
|
if (CPU_EXTENSION_RISCV_C = true) then
|
if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address?
|
if (fetch_engine.restart = '1') then
|
issue_engine.align <= '1'; -- aligned on 16-bit boundary
|
issue_engine.align <= execute_engine.pc(1); -- branch to unaligned address?
|
issue_engine.realign <= '1';
|
elsif (execute_engine.state = DISPATCH) then
|
else
|
issue_engine.align <= (issue_engine.align and (not issue_engine.align_clr)) or issue_engine.align_set;
|
issue_engine.align <= '0'; -- aligned on 32-bit boundary
|
|
issue_engine.realign <= '0';
|
|
end if;
|
end if;
|
else
|
else
|
issue_engine.align <= issue_engine.align_nxt;
|
issue_engine.align <= '0'; -- always aligned
|
issue_engine.realign <= issue_engine.realign_nxt;
|
|
end if;
|
end if;
|
issue_engine.buf <= issue_engine.buf_nxt;
|
|
end if;
|
end if;
|
end process issue_engine_fsm_sync;
|
end process issue_engine_fsm_sync;
|
|
|
|
|
-- Issue Engine FSM Comb ------------------------------------------------------------------
|
-- Issue Engine FSM Comb ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
|
issue_engine_fsm_comb: process(issue_engine.align, ipb)
|
begin
|
begin
|
-- arbiter defaults --
|
-- defaults --
|
issue_engine.realign_nxt <= issue_engine.realign;
|
issue_engine.align_set <= '0';
|
issue_engine.align_nxt <= issue_engine.align;
|
issue_engine.align_clr <= '0';
|
issue_engine.buf_nxt <= issue_engine.buf;
|
issue_engine.valid <= "00";
|
|
|
-- instruction prefetch buffer interface defaults --
|
-- start with LOW half-word --
|
ipb.re <= '0';
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then
|
|
if (CPU_EXTENSION_RISCV_C = true) and (ipb.rdata(0)(1 downto 0) /= "11") then -- compressed
|
-- instruction issue interface defaults --
|
issue_engine.align_set <= ipb.avail(0); -- start of next instruction word is not 32-bit aligned
|
cmd_issue.valid <= '0';
|
issue_engine.valid(0) <= ipb.avail(0);
|
|
issue_engine.data <= issue_engine.ci_ill & ipb.rdata(0)(17 downto 16) & '1' & issue_engine.ci_i32;
|
-- construct instruction data --
|
else -- aligned uncompressed
|
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
|
issue_engine.valid <= (others => (ipb.avail(0) and ipb.avail(1)));
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
|
issue_engine.data <= '0' & (ipb.rdata(1)(17 downto 16) or ipb.rdata(0)(17 downto 16)) &
|
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
|
'0' & (ipb.rdata(1)(15 downto 00) & ipb.rdata(0)(15 downto 00));
|
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
end if;
|
else -- compressed
|
-- start with HIGH half-word --
|
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
else
|
end if;
|
if (CPU_EXTENSION_RISCV_C = true) and (ipb.rdata(1)(1 downto 0) /= "11") then -- compressed
|
else -- not 32-bit aligned
|
issue_engine.align_clr <= ipb.avail(1); -- start of next instruction word is 32-bit aligned again
|
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed
|
issue_engine.valid(1) <= ipb.avail(1);
|
cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
|
issue_engine.data <= issue_engine.ci_ill & ipb.rdata(1)(17 downto 16) & '1' & issue_engine.ci_i32;
|
else -- compressed
|
else -- unaligned uncompressed
|
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
issue_engine.valid <= (others => (ipb.avail(0) and ipb.avail(1)));
|
end if;
|
issue_engine.data <= '0' & (ipb.rdata(0)(17 downto 16) or ipb.rdata(1)(17 downto 16)) &
|
end if;
|
'0' & (ipb.rdata(0)(15 downto 00) & ipb.rdata(1)(15 downto 00));
|
|
|
-- store high half-word - we might need it for an unaligned uncompressed instruction --
|
|
if (execute_engine.state = DISPATCH) and (ipb.avail = '1') and (CPU_EXTENSION_RISCV_C = true) then
|
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
|
|
end if;
|
|
|
|
-- state machine --
|
|
if (ipb.avail = '1') then -- instruction data available?
|
|
|
|
if (issue_engine.realign = '0') then -- issue instruction if available
|
|
-- ------------------------------------------------------------
|
|
cmd_issue.valid <= '1';
|
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
|
|
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
|
|
ipb.re <= '1';
|
|
if (ipb.rdata(1 downto 0) /= "11") and (CPU_EXTENSION_RISCV_C = true) then -- compressed
|
|
issue_engine.align_nxt <= '1';
|
|
end if;
|
|
end if;
|
|
else -- begin check in HIGH instruction half-word
|
|
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
|
|
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and unaligned
|
|
ipb.re <= '1';
|
|
else -- compressed - do not read from ipb here!
|
|
issue_engine.align_nxt <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
else -- re-align input fifo and half-word buffer after a branch to an unaligned address
|
|
-- ------------------------------------------------------------
|
|
ipb.re <= '1';
|
|
issue_engine.realign_nxt <= '0';
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process issue_engine_fsm_comb;
|
end process issue_engine_fsm_comb;
|
|
|
-- 16-bit instructions: half-word select --
|
-- update IPB FIFOs (read-for-next)? --
|
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
|
ipb.re <= issue_engine.valid when (execute_engine.state = DISPATCH) else "00";
|
|
|
|
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
-- Compressed Instructions Decoding -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_decompressor_inst_true:
|
neorv32_cpu_decompressor_inst_true:
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
generic map (
|
generic map (
|
FPU_ENABLE => CPU_EXTENSION_RISCV_Zfinx -- floating-point instruction enabled
|
FPU_ENABLE => CPU_EXTENSION_RISCV_Zfinx -- floating-point instructions enabled
|
)
|
)
|
port map (
|
port map (
|
-- instruction input --
|
-- instruction input --
|
ci_instr16_i => ci_instr16, -- compressed instruction input
|
ci_instr16_i => issue_engine.ci_i16, -- compressed instruction input
|
-- instruction output --
|
-- instruction output --
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
ci_illegal_o => issue_engine.ci_ill, -- illegal compressed instruction
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
ci_instr32_o => issue_engine.ci_i32 -- 32-bit decompressed instruction
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_decompressor_inst_false:
|
neorv32_cpu_decompressor_inst_false:
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
ci_instr32 <= (others => '0');
|
issue_engine.ci_i32 <= (others => '0');
|
ci_illegal <= '0';
|
issue_engine.ci_ill <= '0';
|
end generate;
|
end generate;
|
|
|
|
-- 16-bit instructions: half-word select --
|
|
issue_engine.ci_i16 <= ipb.rdata(0)(15 downto 0) when (issue_engine.align = '0') else ipb.rdata(1)(15 downto 0);
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Execution
|
-- Instruction Execution
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
| Line 686... |
Line 649... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
execute_engine_fsm_sync: process(rstn_i, clk_i)
|
execute_engine_fsm_sync: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
-- no dedicated reset required --
|
-- no dedicated reset required --
|
execute_engine.state_prev <= DISPATCH; -- actual reset value is not relevant
|
execute_engine.state_prev <= BRANCHED; -- actual reset value is not relevant
|
execute_engine.i_reg <= (others => def_rst_val_c);
|
execute_engine.i_reg <= (others => def_rst_val_c);
|
execute_engine.is_ci <= def_rst_val_c;
|
execute_engine.is_ci <= def_rst_val_c;
|
execute_engine.is_ici <= def_rst_val_c;
|
execute_engine.is_ici <= def_rst_val_c;
|
execute_engine.i_reg_last <= (others => def_rst_val_c);
|
execute_engine.i_reg_last <= (others => def_rst_val_c);
|
execute_engine.next_pc <= (others => def_rst_val_c);
|
execute_engine.next_pc <= (others => def_rst_val_c);
|
ctrl <= (others => def_rst_val_c);
|
ctrl <= (others => def_rst_val_c);
|
-- registers that DO require a specific RESET state --
|
-- registers that DO require a specific RESET state --
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned!
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned!
|
execute_engine.pc_last <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00";
|
execute_engine.pc_last <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00";
|
execute_engine.state <= DISPATCH;
|
execute_engine.state <= BRANCHED;
|
execute_engine.sleep <= '0';
|
execute_engine.sleep <= '0';
|
execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
|
execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
|
ctrl(ctrl_bus_rd_c) <= '0';
|
ctrl(ctrl_bus_rd_c) <= '0';
|
ctrl(ctrl_bus_wr_c) <= '0';
|
ctrl(ctrl_bus_wr_c) <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
| Line 714... |
Line 677... |
end if;
|
end if;
|
|
|
-- execute engine arbiter --
|
-- execute engine arbiter --
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state_prev <= execute_engine.state;
|
execute_engine.state_prev <= execute_engine.state;
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
|
execute_engine.branched <= execute_engine.branched_nxt;
|
execute_engine.branched <= execute_engine.branched_nxt;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_ici <= execute_engine.is_ici_nxt;
|
execute_engine.is_ici <= execute_engine.is_ici_nxt;
|
|
|
|
-- sleep mode --
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then
|
|
execute_engine.sleep <= '0'; -- no sleep when in debug mode
|
|
else
|
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
|
end if;
|
|
|
-- PC & IR of "last executed" instruction for trap handling --
|
-- PC & IR of "last executed" instruction for trap handling --
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
execute_engine.pc_last <= execute_engine.pc;
|
execute_engine.pc_last <= execute_engine.pc;
|
execute_engine.i_reg_last <= execute_engine.i_reg;
|
execute_engine.i_reg_last <= execute_engine.i_reg;
|
end if;
|
end if;
|
| Line 734... |
Line 703... |
if (trap_ctrl.cause(5) = '1') and (CPU_EXTENSION_RISCV_DEBUG = true) then -- trap cause: debug mode (re-)entry
|
if (trap_ctrl.cause(5) = '1') and (CPU_EXTENSION_RISCV_DEBUG = true) then -- trap cause: debug mode (re-)entry
|
execute_engine.next_pc <= CPU_DEBUG_ADDR; -- debug mode enter; start at "parking loop" <normal_entry>
|
execute_engine.next_pc <= CPU_DEBUG_ADDR; -- debug mode enter; start at "parking loop" <normal_entry>
|
elsif (debug_ctrl.running = '1') and (CPU_EXTENSION_RISCV_DEBUG = true) then -- any other exception INSIDE debug mode
|
elsif (debug_ctrl.running = '1') and (CPU_EXTENSION_RISCV_DEBUG = true) then -- any other exception INSIDE debug mode
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(CPU_DEBUG_ADDR) + 4); -- start at "parking loop" <exception_entry>
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(CPU_DEBUG_ADDR) + 4); -- start at "parking loop" <exception_entry>
|
else -- normal trapping
|
else -- normal trapping
|
execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
|
execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- trap enter
|
end if;
|
end if;
|
when TRAP_EXIT => -- LEAVING trap environment
|
when TRAP_EXIT => -- LEAVING trap environment
|
if (CPU_EXTENSION_RISCV_DEBUG = false) or (debug_ctrl.running = '0') then -- normal end of trap
|
if (CPU_EXTENSION_RISCV_DEBUG = false) or (debug_ctrl.running = '0') then -- normal end of trap
|
execute_engine.next_pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
|
execute_engine.next_pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
|
else -- DEBUG MODE exiting
|
else -- DEBUG MODE exiting
|
| Line 762... |
Line 731... |
|
|
-- PC output --
|
-- PC output --
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- current PC
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- current PC
|
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- next PC
|
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- next PC
|
|
|
-- CSR access address --
|
|
csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c);
|
|
|
|
|
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, execute_engine, csr, debug_ctrl)
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, execute_engine, csr, debug_ctrl)
|
begin
|
begin
|
| Line 783... |
Line 749... |
-- register addresses --
|
-- register addresses --
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
-- instruction fetch request --
|
-- instruction fetch request --
|
ctrl_o(ctrl_bus_if_c) <= fetch_engine.bus_ir;
|
ctrl_o(ctrl_bus_if_c) <= fetch_engine.bus_if;
|
-- memory access size / sign --
|
-- memory access size / sign --
|
ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
-- alu.shifter --
|
|
ctrl_o(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
|
|
ctrl_o(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
|
|
-- instruction's function blocks (for co-processors) --
|
-- instruction's function blocks (for co-processors) --
|
ctrl_o(ctrl_ir_opcode7_6_c downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c);
|
ctrl_o(ctrl_ir_opcode7_6_c downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c);
|
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
|
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
|
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
-- cpu status --
|
-- cpu status --
|
| Line 900... |
Line 863... |
decode_aux.is_m_div <= '1';
|
decode_aux.is_m_div <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- register/uimm5 checks --
|
-- register/uimm5 checks --
|
decode_aux.rs1_zero <= not or_reduce_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
|
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
decode_aux.rd_zero <= not or_reduce_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c));
|
decode_aux.rs1_zero <= '1';
|
|
else
|
|
decode_aux.rs1_zero <= '0';
|
|
end if;
|
|
if (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") then
|
|
decode_aux.rd_zero <= '1';
|
|
else
|
|
decode_aux.rd_zero <= '0';
|
|
end if;
|
end process decode_helper;
|
end process decode_helper;
|
|
|
|
-- CSR access address --
|
|
csr.addr <= execute_engine.i_reg(instr_imm12_msb_c downto instr_imm12_lsb_c);
|
|
|
|
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, fetch_engine, cmd_issue,
|
execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, fetch_engine, issue_engine,
|
csr, ctrl, alu_idone_i, bus_d_wait_i, excl_state_i)
|
csr, ctrl, alu_idone_i, bus_d_wait_i, excl_state_i)
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
| Line 940... |
Line 913... |
trap_ctrl.env_call <= '0';
|
trap_ctrl.env_call <= '0';
|
trap_ctrl.break_point <= '0';
|
trap_ctrl.break_point <= '0';
|
|
|
-- CSR access --
|
-- CSR access --
|
csr.we_nxt <= '0';
|
csr.we_nxt <= '0';
|
|
csr.re_nxt <= '0';
|
|
|
-- CONTROL DEFAULTS --
|
-- CONTROL DEFAULTS --
|
ctrl_nxt <= (others => '0'); -- default: all off
|
ctrl_nxt <= (others => '0'); -- default: all off
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- default ALU operation: ADD
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- default ALU operation: ADD
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_alu_c; -- default RF input: ALU
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_alu_c; -- default RF input: ALU
|
| Line 960... |
Line 934... |
-- state machine --
|
-- state machine --
|
case execute_engine.state is
|
case execute_engine.state is
|
|
|
when DISPATCH => -- Get new command from instruction issue engine
|
when DISPATCH => -- Get new command from instruction issue engine
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- PC update --
|
-- PC & IR update --
|
execute_engine.pc_mux_sel <= '0'; -- linear next PC
|
execute_engine.pc_mux_sel <= '0'; -- linear next PC
|
-- IR update --
|
execute_engine.i_reg_nxt <= issue_engine.data(31 downto 0);
|
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction
|
execute_engine.is_ci_nxt <= issue_engine.data(32); -- this is a de-compressed instruction
|
execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
|
execute_engine.is_ici_nxt <= issue_engine.data(35); -- illegal compressed instruction
|
--
|
--
|
if (cmd_issue.valid = '1') then -- instruction available?
|
if (issue_engine.valid(0) = '1') or (issue_engine.valid(1) = '1') then -- instruction available?
|
-- PC update --
|
-- PC update --
|
execute_engine.branched_nxt <= '0';
|
execute_engine.branched_nxt <= '0';
|
execute_engine.pc_we <= not execute_engine.branched; -- update PC with linear next_pc if there was no actual branch
|
execute_engine.pc_we <= not execute_engine.branched; -- update PC with linear next_pc if there was no actual branch
|
-- IR update - exceptions --
|
-- IR update - exceptions --
|
if (CPU_EXTENSION_RISCV_C = false) then
|
trap_ctrl.instr_ma <= issue_engine.data(33) and (not bool_to_ulogic_f(CPU_EXTENSION_RISCV_C)); -- misaligned instruction fetch (if C disabled)
|
trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address, if C disabled
|
trap_ctrl.instr_be <= issue_engine.data(34); -- bus access fault during instruction fetch
|
end if;
|
|
trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instruction fetch
|
|
execute_engine.is_ici_nxt <= cmd_issue.data(35); -- invalid decompressed instruction
|
|
-- any reason to go to trap state? --
|
-- any reason to go to trap state? --
|
if (execute_engine.sleep = '1') or -- enter sleep state
|
if (execute_engine.sleep = '1') or -- enter sleep state
|
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (e.g. illegal instruction)
|
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (e.g. illegal instruction)
|
(trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception)
|
(trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception)
|
((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address (if C disabled)
|
((issue_engine.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address (if C disabled)
|
(cmd_issue.data(34) = '1') then -- bus access fault during instruction fetch
|
(issue_engine.data(34) = '1') then -- bus access fault during instruction fetch
|
execute_engine.state_nxt <= TRAP_ENTER;
|
execute_engine.state_nxt <= TRAP_ENTER;
|
else
|
else
|
execute_engine.state_nxt <= EXECUTE;
|
execute_engine.state_nxt <= EXECUTE;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
when TRAP_ENTER => -- Start trap environment - get trap vector (depc or epc), stay here for sleep mode
|
when TRAP_ENTER => -- Start trap environment - get trap vector, stay here for sleep mode
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
trap_ctrl.env_start_ack <= '1';
|
trap_ctrl.env_start_ack <= '1';
|
execute_engine.state_nxt <= TRAP_EXECUTE;
|
execute_engine.state_nxt <= TRAP_EXECUTE;
|
end if;
|
end if;
|
| Line 1003... |
Line 974... |
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
trap_ctrl.env_end <= '1';
|
trap_ctrl.env_end <= '1';
|
execute_engine.state_nxt <= TRAP_EXECUTE;
|
execute_engine.state_nxt <= TRAP_EXECUTE;
|
|
|
|
|
when TRAP_EXECUTE => -- Process trap environment -> jump to xTVEC / return from trap environment -> jump to xEPC
|
when TRAP_EXECUTE => -- Process trap environment
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= '0'; -- next_PC
|
execute_engine.pc_mux_sel <= '0'; -- next_PC (or xEPC / trap vector)
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.sleep_nxt <= '0'; -- disable sleep mode
|
execute_engine.sleep_nxt <= '0'; -- disable sleep mode
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= BRANCHED;
|
|
|
|
|
when EXECUTE => -- Decode and execute instruction (control has to be here for exactly 1 cycle in any case!)
|
when EXECUTE => -- Decode and execute instruction (control has to be here for exactly 1 cycle in any case!)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
case opcode_v is
|
|
|
|
when opcode_alu_c | opcode_alui_c => -- (register/immediate) ALU operation
|
when opcode_alu_c | opcode_alui_c => -- (register/immediate) ALU operation
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= not execute_engine.i_reg(instr_opcode_msb_c-1); -- use IMM as ALU.OPB for immediate operations
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= not execute_engine.i_reg(instr_opcode_msb_c-1); -- use IMM as ALU.OPB for immediate operations
|
|
|
| Line 1042... |
Line 1012... |
end case;
|
end case;
|
|
|
-- co-processor MULDIV operation (multi-cycle) --
|
-- co-processor MULDIV operation (multi-cycle) --
|
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
|
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
|
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
|
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- trigger MULDIV CP
|
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_muldiv_c; -- trigger MULDIV CP
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
-- co-processor BIT-MANIPULATION operation (multi-cycle) --
|
-- co-processor BIT-MANIPULATION operation (multi-cycle) --
|
elsif (CPU_EXTENSION_RISCV_B = true) and
|
elsif (CPU_EXTENSION_RISCV_B = true) and
|
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation
|
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation
|
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation
|
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- trigger BITMANIP CP
|
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_bitmanip_c; -- trigger BITMANIP CP
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
-- co-processor SHIFT operation (multi-cycle) --
|
-- co-processor SHIFT operation (multi-cycle) --
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- trigger SHIFTER CP
|
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_shifter_c; -- trigger SHIFTER CP
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
-- ALU CORE operation (single-cycle) --
|
-- ALU CORE operation (single-cycle) --
|
else
|
else
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
| Line 1095... |
Line 1065... |
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
|
|
when opcode_fence_c => -- fence operations
|
when opcode_fence_c => -- fence operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c+1) = funct3_fence_c(2 downto 1)) then -- FENCE / FENCE.I
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
ctrl_nxt(ctrl_bus_fence_c) <= not execute_engine.i_reg(instr_funct3_lsb_c); -- FENCE
|
execute_engine.state_nxt <= DISPATCH;
|
ctrl_nxt(ctrl_bus_fencei_c) <= execute_engine.i_reg(instr_funct3_lsb_c) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- FENCE.I
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
|
execute_engine.branched_nxt <= '1'; -- this is an actual branch
|
|
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC)
|
|
else -- illegal fence instruction
|
|
execute_engine.state_nxt <= DISPATCH;
|
|
end if;
|
end if;
|
|
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC)
|
|
|
|
|
when opcode_fop_c => -- floating-point operations
|
when opcode_fop_c => -- floating-point operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zfinx = true) then
|
if (CPU_EXTENSION_RISCV_Zfinx = true) then
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
|
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_fpu_c; -- trigger FPU CP
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
else
|
else
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when opcode_cust0_c => -- CFU: custom RISC-V instructions (CUSTOM0 OPCODE space)
|
when opcode_cust0_c => -- CFU: custom RISC-V instructions (CUSTOM0 OPCODE space)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zxcfu = true) then
|
if (CPU_EXTENSION_RISCV_Zxcfu = true) then
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_cfu_c; -- trigger CFU CP
|
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_cfu_c; -- trigger CFU CP
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
else
|
else
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when others => -- system/csr access OR illegal opcode
|
when opcode_system_c => -- environment/csr access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
csr.re_nxt <= '1'; -- always read CSR, only relevant for CSR access
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
execute_engine.state_nxt <= SYSTEM;
|
execute_engine.state_nxt <= SYS_ENV;
|
|
else -- CSR access
|
|
execute_engine.state_nxt <= CSR_ACCESS;
|
|
end if;
|
|
else
|
else
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
end case;
|
|
|
|
|
|
when SYS_ENV => -- system environment operation
|
when others => -- illegal opcode
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- MRET / DRET --
|
execute_engine.state_nxt <= DISPATCH;
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) then
|
|
execute_engine.state_nxt <= TRAP_EXIT; -- mret
|
end case; -- /EXECUTE
|
elsif (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_dret_c) and
|
|
(CPU_EXTENSION_RISCV_DEBUG = true) then
|
|
debug_ctrl.dret <= '1';
|
|
execute_engine.state_nxt <= TRAP_EXIT; -- dret
|
|
else
|
|
execute_engine.state_nxt <= DISPATCH; -- default
|
|
end if;
|
|
-- ECALL / EBREAK --
|
|
if ((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c+1) = funct12_ecall_c(11 downto 1))) then
|
|
if (execute_engine.i_reg(instr_funct12_lsb_c) = funct12_ecall_c(0)) then
|
|
trap_ctrl.env_call <= '1'; -- ecall
|
|
else
|
|
trap_ctrl.break_point <= '1'; -- ebreak
|
|
end if;
|
|
end if;
|
|
-- WFI --
|
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) and
|
|
((CPU_EXTENSION_RISCV_DEBUG = false) or ((debug_ctrl.running = '0') and (csr.dcsr_step = '0'))) then
|
|
execute_engine.sleep_nxt <= '1'; -- not executed (NOP) when in debug-mode or during single-stepping
|
|
end if;
|
|
|
|
|
|
when CSR_ACCESS => -- read & write status and control register (CSR) - no read/write if illegal instruction
|
when SYSTEM => -- system environment operation
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- CSR write access [invalid CSR instructions are already checked by the illegal instruction logic] --
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_csr_c; -- only relevant for CSR access
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
execute_engine.state_nxt <= DISPATCH; -- default
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or -- CSRRW(I); always write CSR
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) and -- ENVIRONMENT
|
(decode_aux.rs1_zero = '0') then -- CSRRS(I) / CSRRC(I): write CSR if rs1/imm5 is NOT zero
|
(trap_ctrl.exc_buf(exc_iillegal_c) = '0') then -- and NOT already identified as illegal instruction
|
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
|
when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ecall
|
|
when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- ebreak
|
|
when funct12_mret_c => execute_engine.state_nxt <= TRAP_EXIT; -- mret
|
|
when funct12_dret_c => execute_engine.state_nxt <= TRAP_EXIT; debug_ctrl.dret <= '1'; -- dret
|
|
when others => execute_engine.sleep_nxt <= '1'; -- "funct12_wfi_c" - wfi/sleep
|
|
end case;
|
|
else -- CSR ACCESS - there will be no state change if illegal instruction
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or -- CSRRW: always write CSR
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or -- CSRRWI: always write CSR
|
|
(decode_aux.rs1_zero = '0') then -- CSRR(S/C)(I): write CSR if rs1/imm5 is NOT zero
|
csr.we_nxt <= '1';
|
csr.we_nxt <= '1';
|
end if;
|
end if;
|
-- register file write back --
|
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_csr_c;
|
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
|
|
|
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (ALU co-processor) to finish
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (ALU co-processor) to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_cp_c;
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_cp_c;
|
| Line 1193... |
Line 1142... |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (won't happen in case of an illegal instruction)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (won't happen in case of an illegal instruction)
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when BRANCH => -- update PC for taken branches and jumps
|
when BRANCH => -- update PC on taken branches and jumps
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- get and store return address (only relevant for jump-and-link operations) --
|
-- get and store return address (only relevant for jump-and-link operations) --
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_npc_c; -- next PC
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_npc_c; -- next PC
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
|
-- destination address --
|
-- destination address --
|
execute_engine.pc_mux_sel <= '1'; -- PC <= alu.add = branch/jump destination
|
execute_engine.pc_mux_sel <= '1'; -- PC <= alu.add = branch/jump destination
|
|
execute_engine.pc_we <= '1'; -- update PC with destination; will be overridden again in DISPATCH if branch not taken
|
if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
|
if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
|
-- no need to check for illegal instructions here; the branch condition evaluation circuit will not set "branch_taken" if funct3 is invalid
|
fetch_engine.reset <= '1'; -- reset instruction fetch starting at modified PC
|
execute_engine.pc_we <= '1'; -- update PC
|
execute_engine.state_nxt <= BRANCHED;
|
execute_engine.branched_nxt <= '1'; -- this is an actual branch
|
else
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
|
when BRANCHED => -- delay cycle to wait for reset of pipeline front-end
|
|
-- ------------------------------------------------------------
|
|
execute_engine.branched_nxt <= '1'; -- this is an actual branch
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
|
|
when LOADSTORE_0 => -- trigger memory request
|
when LOADSTORE_0 => -- trigger memory request
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_a_lr; -- atomic.LR: set lock
|
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_a_lr = '1') then -- normal load or atomic load-reservate
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_a_lr = '1') then -- normal load or atomic load-reservate
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- bus read request
|
else -- store
|
elsif (decode_aux.is_a_sc = '0') or (excl_state_i = '1') then -- normal store request or atomic store-conditional with lock still OK
|
if (decode_aux.is_a_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- bus write request
|
ctrl_nxt(ctrl_bus_wr_c) <= '1';
|
|
else -- evaluate lock state
|
|
ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok
|
|
end if;
|
|
end if;
|
end if;
|
|
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_a_lr; -- atomic load-reservate: set lock
|
execute_engine.state_nxt <= LOADSTORE_1;
|
execute_engine.state_nxt <= LOADSTORE_1;
|
|
|
|
|
when LOADSTORE_1 => -- memory access latency
|
when LOADSTORE_1 => -- memory access latency
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOADs)
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for load and SC.W operations)
|
execute_engine.state_nxt <= LOADSTORE_2;
|
execute_engine.state_nxt <= LOADSTORE_2;
|
|
|
|
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load (and SC.W) operations)
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load and SC.W operations)
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_mem_c; -- memory read data
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_mem_c; -- memory read data
|
-- wait for memory response --
|
-- wait for memory response --
|
if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related
|
if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
| Line 1366... |
Line 1317... |
|
|
|
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
illegal_instruction_check: process(execute_engine, decode_aux, csr, csr_acc_valid, debug_ctrl)
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illegal_instruction_check: process(execute_engine, decode_aux, csr, csr_acc_valid, debug_ctrl)
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variable opcode_v : std_ulogic_vector(6 downto 0);
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begin
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begin
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-- defaults --
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-- defaults --
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illegal_instruction <= '0';
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illegal_cmd <= '0';
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illegal_register <= '0';
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illegal_reg <= '0';
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-- check opcode for rv32 --
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-- check instruction word encoding and side effects --
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if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then
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case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
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illegal_opcode_lsbs <= '0';
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else
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illegal_opcode_lsbs <= '1';
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end if;
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-- check for illegal compressed instruction --
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when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- LUI, UIPC, JAL (only check actual OPCODE)
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if (CPU_EXTENSION_RISCV_C = true) then
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-- ------------------------------------------------------------
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illegal_compressed <= execute_engine.is_ici;
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illegal_cmd <= '0';
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else
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illegal_reg <= execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
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illegal_compressed <= '0';
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end if;
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-- check instructions --
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when opcode_jalr_c => -- check JALR.funct3
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opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
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-- ------------------------------------------------------------
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case opcode_v is
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
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when "000" => illegal_cmd <= '0';
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when others => illegal_cmd <= '1';
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end case;
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illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
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when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- check sufficient LUI, UIPC, JAL (only check actual OPCODE)
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when opcode_branch_c => -- check BRANCH.funct3
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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illegal_instruction <= '0';
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
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-- illegal E-CPU register? --
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when funct3_beq_c | funct3_bne_c | funct3_blt_c | funct3_bge_c | funct3_bltu_c | funct3_bgeu_c => illegal_cmd <= '0';
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illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
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when others => illegal_cmd <= '1';
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end case;
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illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c); -- illegal 'E' register?
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when opcode_load_c => -- check LOAD.funct3
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-- ------------------------------------------------------------
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
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when funct3_lb_c | funct3_lh_c | funct3_lw_c | funct3_lbu_c | funct3_lhu_c => illegal_cmd <= '0';
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when others => illegal_cmd <= '1';
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end case;
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illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
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when opcode_store_c => -- check STORE.funct3
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-- ------------------------------------------------------------
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
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when funct3_sb_c | funct3_sh_c | funct3_sw_c => illegal_cmd <= '0';
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when others => illegal_cmd <= '1';
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end case;
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illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c); -- illegal 'E' register?
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when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
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when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and
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if ((((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and
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(execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or
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(execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or
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(((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
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(((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c)) and
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c)) and
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(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) then -- valid base ALUI instruction?
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(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000"))) or -- valid base ALU instruction?
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illegal_instruction <= '0';
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(((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true)) and (decode_aux.is_m_mul = '1')) or -- valid MUL instruction?
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elsif ((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = false)) and (decode_aux.is_m_mul = '1') then -- valid MUL instruction?
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((CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1')) or -- valid DIV instruction?
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illegal_instruction <= '0';
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((CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_reg = '1')) then -- valid BITMANIP register instruction?
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elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction?
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illegal_cmd <= '0';
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illegal_instruction <= '0';
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elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_reg = '1') then -- valid BITMANIP instruction?
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illegal_instruction <= '0';
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else
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else
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illegal_instruction <= '1';
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illegal_cmd <= '1';
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end if;
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end if;
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-- illegal E-CPU register? --
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illegal_reg <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c); -- illegal 'E' register?
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illegal_register <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c);
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when opcode_alui_c => -- check ALUI.funct7
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when opcode_alui_c => -- check ALU.funct3 & ALU.funct7
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
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if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c) or
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((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and -- shift logical left
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((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
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(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or
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(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or
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((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right
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((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
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((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction?
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((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')))) or -- valid base ALUI instruction?
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illegal_instruction <= '0';
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((CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_imm = '1')) then -- valid BITMANIP immediate instruction?
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elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_imm = '1') then -- valid BITMANIP immediate instruction?
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illegal_cmd <= '0';
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illegal_instruction <= '0';
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else
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else
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illegal_instruction <= '1';
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illegal_cmd <= '1';
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end if;
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end if;
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-- illegal E-CPU register? --
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illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
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illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
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when opcode_load_c => -- check LOAD.funct3
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when opcode_fence_c => -- check FENCE.funct3, ignore all remaining bit-fields
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
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when funct3_fence_c => illegal_cmd <= '0'; -- FENCE
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
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when funct3_fencei_c => illegal_cmd <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- FENCE.I
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
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when others => illegal_cmd <= '1';
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
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end case;
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illegal_instruction <= '0';
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else
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illegal_instruction <= '1';
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end if;
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-- illegal E-CPU register? --
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illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
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when opcode_store_c => -- check STORE.funct3
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
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illegal_instruction <= '0';
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else
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illegal_instruction <= '1';
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end if;
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-- illegal E-CPU register? --
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illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
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when opcode_atomic_c => -- atomic instructions
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-- ------------------------------------------------------------
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if (CPU_EXTENSION_RISCV_A = true) then
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if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR
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illegal_instruction <= '0';
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-- illegal E-CPU register? --
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illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
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elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC
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illegal_instruction <= '0';
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-- illegal E-CPU register? --
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illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
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else
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illegal_instruction <= '1';
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end if;
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else
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illegal_instruction <= '1';
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end if;
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when opcode_branch_c => -- check BRANCH.funct3
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when opcode_atomic_c => -- check AMO.funct3 and AMO.funct5
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
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if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") and
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
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(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c+1) = "0001") then -- LR/SC
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
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illegal_cmd <= '0';
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
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else
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
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illegal_cmd <= '1';
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
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end if;
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illegal_instruction <= '0';
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illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
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when opcode_system_c => -- check system instructions
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system environment
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if (decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') then
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case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
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when funct12_ecall_c | funct12_ebreak_c => illegal_cmd <= '0'; -- ECALL, EBREAK
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when funct12_mret_c => illegal_cmd <= not csr.privilege; -- MRET (only allowed in ACTUAL M-mode)
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when funct12_wfi_c => illegal_cmd <= (not csr.privilege) and csr.mstatus_tw; -- WFI (only allowed in ACTUAL M-mode or if mstatus.TW = 0)
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when funct12_dret_c => illegal_cmd <= not debug_ctrl.running; -- DRET (only allowed in D-mode)
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when others => illegal_cmd <= '1';
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end case;
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else
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else
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illegal_instruction <= '1';
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illegal_cmd <= '1';
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end if;
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end if;
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-- illegal E-CPU register? --
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else -- CSR access
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illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
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if (csr_acc_valid = '0') then -- invalid CSR access?
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illegal_cmd <= '1';
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when opcode_jalr_c => -- check JALR.funct3
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
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illegal_instruction <= '0';
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else
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illegal_instruction <= '1';
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end if;
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end if;
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-- illegal E-CPU register? --
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illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
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when opcode_fence_c => -- check FENCE.funct3
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-- ------------------------------------------------------------
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if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true)) or -- FENCE.I
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
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illegal_instruction <= '0';
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else
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illegal_instruction <= '1';
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end if;
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end if;
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-- NOTE: ignore all remaining bit fields here
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when opcode_syscsr_c => -- check system instructions
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|
-- ------------------------------------------------------------
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-- CSR access --
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|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c)) and
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|
(csr_acc_valid = '1') then -- valid CSR access?
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|
illegal_instruction <= '0';
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|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR (or ENV where rd=rs1=zero)
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illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
illegal_reg <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
|
else -- reg-imm CSR
|
else -- reg-imm CSR
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illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
illegal_reg <= execute_engine.i_reg(instr_rd_msb_c);
|
end if;
|
|
-- system: ecall, ebreak, mret, wfi, dret --
|
|
-- > WFI is always allowed to execute in M-mode; in U-mode it is allowed to execute if mstatus.TW = 0
|
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and
|
|
(decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) and (csr.privilege = priv_mode_m_c)) or -- MRET (only allowed in ACTUAL M-mode)
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_dret_c) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or -- DRET (only allowed in D-mode)
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) and ((csr.privilege = priv_mode_m_c) or (csr.mstatus_tw = '0')))) then -- WFI
|
|
illegal_instruction <= '0';
|
|
else
|
|
illegal_instruction <= '1';
|
|
end if;
|
end if;
|
|
|
when opcode_fop_c => -- floating point operations - single/dual operands
|
when opcode_fop_c => -- floating point operations - single/dual operands
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
|
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
|
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
|
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
|
(decode_aux.is_f_op = '1') then -- is correct/supported floating-point instruction
|
(decode_aux.is_f_op = '1') then -- is correct/supported floating-point instruction
|
illegal_instruction <= '0';
|
illegal_cmd <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_cmd <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
-- FIXME: rs2 is not checked!
|
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
|
|
|
when opcode_cust0_c => -- CFU: custom instructions
|
when opcode_cust0_c => -- CFU: custom instructions
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zxcfu = true) then -- CFU extension implemented
|
illegal_cmd <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- CFU extension not implemented
|
illegal_instruction <= '0';
|
illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
else
|
|
illegal_instruction <= '1';
|
|
end if;
|
|
-- illegal E-CPU register? --
|
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
|
|
|
when others => -- undefined instruction -> illegal!
|
when others => -- illegal opcode
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
illegal_instruction <= '1';
|
illegal_cmd <= '1';
|
|
|
end case;
|
end case;
|
end process illegal_instruction_check;
|
end process illegal_instruction_check;
|
|
|
|
|
-- Illegal Operation Check ----------------------------------------------------------------
|
-- Illegal Operation Check ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- check in EXECUTE state: any illegal condition? --
|
-- check in EXECUTE state: any illegal condition? --
|
trap_ctrl.instr_il <= (illegal_opcode_lsbs or -- illegal opcode LSB bits - not rv32
|
trap_ctrl.instr_il <= (illegal_cmd or -- illegal instruction
|
illegal_instruction or -- illegal instruction
|
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and illegal_reg) or -- illegal register access in E extension
|
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and illegal_register) or -- illegal register access in E extension
|
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_C) and execute_engine.is_ici)) -- illegal compressed instruction
|
illegal_compressed) -- illegal compressed instruction
|
when (execute_engine.state = EXECUTE) else '0'; -- evaluate in EXECUTE stage only
|
when (execute_engine.state = EXECUTE) else '0';
|
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Exception and Interrupt (= Traps) Control
|
-- Exception and Interrupt (= Traps) Control
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Trap Controller ------------------------------------------------------------------------
|
-- Trap Controller ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_controller: process(rstn_i, clk_i)
|
trap_controller: process(rstn_i, clk_i)
|
variable mode_m_v, mode_u_v : std_ulogic;
|
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
| Line 1665... |
Line 1550... |
end if;
|
end if;
|
end if;
|
end if;
|
end process trap_controller;
|
end process trap_controller;
|
|
|
-- any exception/interrupt? --
|
-- any exception/interrupt? --
|
trap_ctrl.exc_fire <= or_reduce_f(trap_ctrl.exc_buf); -- sync. exceptions CANNOT be masked
|
trap_ctrl.exc_fire <= '1' when (or_reduce_f(trap_ctrl.exc_buf) = '1') else '0'; -- sync. exceptions CANNOT be masked
|
trap_ctrl.irq_fire <= (or_reduce_f(trap_ctrl.irq_buf) and csr.mstatus_mie and trap_ctrl.db_irq_en) or trap_ctrl.db_irq_fire; -- interrupts CAN be masked (but not the DEBUG halt IRQ)
|
trap_ctrl.irq_fire <= '1' when ((or_reduce_f(trap_ctrl.irq_buf) = '1') and (csr.mstatus_mie = '1') and (trap_ctrl.db_irq_en = '1')) or -- interrupts CAN be masked
|
|
(trap_ctrl.db_irq_fire = '1') else '0'; -- but not the DEBUG halt IRQ
|
|
|
-- debug mode (entry) interrupts --
|
-- debug mode (entry) interrupts --
|
trap_ctrl.db_irq_en <= '0' when (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) else '1'; -- no interrupts when IN debug mode or IN single-step mode
|
trap_ctrl.db_irq_en <= '0' when (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) else '1'; -- no interrupts when IN debug mode or IN single-step mode
|
trap_ctrl.db_irq_fire <= (trap_ctrl.irq_buf(irq_db_step_c) or trap_ctrl.irq_buf(irq_db_halt_c)) when (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; -- "NMI" for debug mode entry
|
trap_ctrl.db_irq_fire <= (trap_ctrl.irq_buf(irq_db_step_c) or trap_ctrl.irq_buf(irq_db_halt_c)) when (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; -- "NMI" for debug mode entry
|
|
|
| Line 1856... |
Line 1742... |
when funct3_csrrs_c => csr.wdata <= csr.rdata or rs1_i;
|
when funct3_csrrs_c => csr.wdata <= csr.rdata or rs1_i;
|
when funct3_csrrc_c => csr.wdata <= csr.rdata and (not rs1_i);
|
when funct3_csrrc_c => csr.wdata <= csr.rdata and (not rs1_i);
|
when funct3_csrrwi_c => csr.wdata <= csr_imm_v;
|
when funct3_csrrwi_c => csr.wdata <= csr_imm_v;
|
when funct3_csrrsi_c => csr.wdata <= csr.rdata or csr_imm_v;
|
when funct3_csrrsi_c => csr.wdata <= csr.rdata or csr_imm_v;
|
when funct3_csrrci_c => csr.wdata <= csr.rdata and (not csr_imm_v);
|
when funct3_csrrci_c => csr.wdata <= csr.rdata and (not csr_imm_v);
|
when others => csr.wdata <= (others => '-'); -- undefined
|
when others => csr.wdata <= (others => '0'); -- undefined
|
end case;
|
end case;
|
end process csr_write_data;
|
end process csr_write_data;
|
|
|
|
|
-- Control and Status Registers - Write Access --------------------------------------------
|
-- Control and Status Registers - Write Access --------------------------------------------
|
| Line 1868... |
Line 1754... |
csr_write_access: process(rstn_i, clk_i)
|
csr_write_access: process(rstn_i, clk_i)
|
variable cause_v : std_ulogic_vector(6 downto 0);
|
variable cause_v : std_ulogic_vector(6 downto 0);
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
csr.we <= '0';
|
csr.we <= '0';
|
|
csr.re <= def_rst_val_c;
|
--
|
--
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpp <= '0';
|
csr.mstatus_mpp <= '0';
|
csr.mstatus_tw <= '0';
|
csr.mstatus_tw <= '0';
|
| Line 1914... |
Line 1801... |
csr.tdata1_exe <= '0';
|
csr.tdata1_exe <= '0';
|
csr.tdata2 <= (others => def_rst_val_c);
|
csr.tdata2 <= (others => def_rst_val_c);
|
|
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- write access? --
|
-- write access? --
|
csr.we <= csr.we_nxt;
|
csr.we <= csr.we_nxt and (not trap_ctrl.exc_buf(exc_iillegal_c)); -- write if not illegal instruction
|
|
csr.re <= csr.re_nxt;
|
|
|
-- defaults --
|
-- defaults --
|
csr.mip_firq_nclr <= (others => '1'); -- active low
|
csr.mip_firq_nclr <= (others => '1'); -- active low
|
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSR access by application software
|
-- CSR access by application software
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
if (csr.we = '1') and (trap_ctrl.exc_buf(exc_iillegal_c) = '0') then -- manual write access and not illegal instruction
|
if (csr.we = '1') then -- manual write access and not illegal instruction
|
|
|
-- user floating-point CSRs --
|
-- user floating-point CSRs --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- floating point CSR class
|
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- floating point CSR class
|
if (csr.addr(11 downto 2) = csr_class_float_c) then
|
if (csr.addr(11 downto 2) = csr_class_float_c) then
|
| Line 1986... |
Line 1874... |
if (csr.addr(3 downto 0) = csr_mepc_c(3 downto 0)) then
|
if (csr.addr(3 downto 0) = csr_mepc_c(3 downto 0)) then
|
csr.mepc <= csr.wdata;
|
csr.mepc <= csr.wdata;
|
end if;
|
end if;
|
-- R/W: mcause - machine trap cause --
|
-- R/W: mcause - machine trap cause --
|
if (csr.addr(3 downto 0) = csr_mcause_c(3 downto 0)) then
|
if (csr.addr(3 downto 0) = csr_mcause_c(3 downto 0)) then
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: async/interrupt, 0: sync/exception
|
csr.mcause <= csr.wdata(31) & csr.wdata(4 downto 0); -- type + identifier
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
|
end if;
|
end if;
|
-- R/W: mip - machine interrupt pending --
|
-- R/W: mip - machine interrupt pending --
|
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
|
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
|
csr.mip_firq_nclr <= csr.wdata(31 downto 16); -- set low to clear according bit (FIRQs only)
|
csr.mip_firq_nclr <= csr.wdata(31 downto 16); -- set low to clear according bit (FIRQs only)
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
|
-- physical memory protection --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (PMP_NUM_REGIONS > 0) then
|
if (PMP_NUM_REGIONS > 0) then
|
|
-- R/W: pmpcfg* - PMP configuration registers --
|
if (csr.addr(11 downto 2) = csr_class_pmpcfg_c) then -- pmp configuration CSR class
|
if (csr.addr(11 downto 2) = csr_class_pmpcfg_c) then -- pmp configuration CSR class
|
for i in 0 to 3 loop -- 3 pmpcfg CSRs
|
for i in 0 to 3 loop -- 3 pmpcfg CSRs
|
if (csr.addr(1 downto 0) = std_ulogic_vector(to_unsigned(i, 2))) then
|
if (csr.addr(1 downto 0) = std_ulogic_vector(to_unsigned(i, 2))) then
|
for j in 0 to 3 loop -- 4 entries per CSR
|
for j in 0 to 3 loop -- 4 entries per CSR
|
if (csr.pmpcfg(i*4+j)(7) = '0') then -- unlocked pmpcfg entry
|
if (csr.pmpcfg(i*4+j)(7) = '0') then -- unlocked pmpcfg entry
|
| Line 2016... |
Line 1904... |
end if;
|
end if;
|
end loop; -- j (entry)
|
end loop; -- j (entry)
|
end if;
|
end if;
|
end loop; -- i (pmpcfg CSR)
|
end loop; -- i (pmpcfg CSR)
|
end if;
|
end if;
|
end if;
|
-- R/W: pmpaddr* - PMP address registers --
|
|
|
-- physical memory protection: R/W: pmpaddr* - PMP address registers --
|
|
-- --------------------------------------------------------------------
|
|
if (PMP_NUM_REGIONS > 0) then
|
|
if (csr.addr(11 downto 4) = csr_class_pmpaddr_c) then
|
if (csr.addr(11 downto 4) = csr_class_pmpaddr_c) then
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
csr.pmpaddr(i) <= csr.wdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2);
|
csr.pmpaddr(i) <= csr.wdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2);
|
end if;
|
end if;
|
| Line 2116... |
Line 2000... |
-- normal trap entry: write mcause, mepc and mtval --
|
-- normal trap entry: write mcause, mepc and mtval --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and (debug_ctrl.running = '0')) then
|
if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and (debug_ctrl.running = '0')) then
|
|
|
-- trap cause ID code --
|
-- trap cause ID code --
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
csr.mcause <= trap_ctrl.cause(trap_ctrl.cause'left) & trap_ctrl.cause(4 downto 0); -- type + identifier
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
|
|
|
-- trap PC --
|
-- trap PC --
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source)
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source)
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
else -- for sync. EXCEPTIONS (sync source)
|
else -- for sync. EXCEPTIONS (sync source)
|
csr.mepc <= execute_engine.pc_last(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
csr.mepc <= execute_engine.pc_last(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
end if;
|
end if;
|
|
|
-- trap value --
|
-- trap value --
|
cause_v := trap_ctrl.cause;
|
cause_v := trap_ctrl.cause;
|
cause_v(5) := '0'; -- bit 5 is always zero here (= normal trapping), so we do not need to check that again
|
cause_v(5) := '0'; -- bit 5 is always zero here (= normal trapping / no debug-mode-entry), so we do not need to check that again
|
case cause_v is
|
case cause_v is
|
when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
|
when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
when trap_brk_c => -- breakpoint
|
|
csr.mtval <= execute_engine.pc_last(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction
|
|
when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
|
when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
|
csr.mtval <= mar_i; -- faulting data access address
|
csr.mtval <= mar_i; -- faulting data access address
|
when trap_iil_c => -- illegal instruction
|
when trap_iil_c => -- illegal instruction
|
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
|
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction word (decompressed if C-instruction)
|
when others => -- everything else including all interrupts
|
when others => -- everything else including all interrupts
|
csr.mtval <= (others => '0');
|
csr.mtval <= (others => '0');
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
| Line 2214... |
Line 2095... |
end generate;
|
end generate;
|
|
|
|
|
-- Control and Status Registers - Read Access ---------------------------------------------
|
-- Control and Status Registers - Read Access ---------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_read_access: process(rstn_i, clk_i)
|
csr_read_access: process(clk_i)
|
variable csr_addr_v : std_ulogic_vector(11 downto 0);
|
variable csr_addr_v : std_ulogic_vector(11 downto 0);
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs are hardwired to zero
|
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs read as zero
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
|
|
|
-- AND-gate CSR read address: csr.rdata is zero if csr.re is not set --
|
|
if (csr.re = '1') then
|
csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
|
csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
|
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) CSRs ONLY !!!
|
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) CSRS ONLY !!!
|
csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
|
csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
|
|
else -- reduce switching activity if not accessed
|
|
csr_addr_v := (others => '0'); -- = csr_zero_c
|
|
end if;
|
case csr_addr_v is
|
case csr_addr_v is
|
|
|
|
-- hardware-only CSRs --
|
|
-- --------------------------------------------------------------------
|
|
-- when csr_zero_c => -- zero (r/-): always returns zero, only relevant for hardware-access, not visible to ISA
|
|
-- csr.rdata <= (others => '0');
|
|
|
-- floating-point CSRs --
|
-- floating-point CSRs --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_fflags_c => -- fflags (r/w): floating-point (FPU) exception flags
|
when csr_fflags_c => -- fflags (r/w): floating-point (FPU) exception flags
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if;
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if;
|
when csr_frm_c => -- frm (r/w): floating-point (FPU) rounding mode
|
when csr_frm_c => -- frm (r/w): floating-point (FPU) rounding mode
|
| Line 2236... |
Line 2128... |
when csr_fcsr_c => -- fcsr (r/w): floating-point (FPU) control/status (frm + fflags)
|
when csr_fcsr_c => -- fcsr (r/w): floating-point (FPU) control/status (frm + fflags)
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(7 downto 0) <= csr.frm & csr.fflags; else NULL; end if;
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(7 downto 0) <= csr.frm & csr.fflags; else NULL; end if;
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_mstatus_c => -- mstatus (r/w): machine status register
|
when csr_mstatus_c => -- mstatus (r/w): machine status register - low word
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(12 downto 11) <= (others => csr.mstatus_mpp); -- MPP: machine previous privilege mode
|
csr.rdata(12 downto 11) <= (others => csr.mstatus_mpp); -- MPP: machine previous privilege mode
|
csr.rdata(21) <= csr.mstatus_tw and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- TW
|
csr.rdata(21) <= csr.mstatus_tw and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- TW
|
-- when csr_mstatush_c => -- mstatush (r/w): machine status register - high, implemented but always zero
|
-- when csr_mstatush_c => -- mstatush (r/w): machine status register - high word, implemented but always zero
|
-- csr.rdata <= (others => '0');
|
-- csr.rdata <= (others => '0');
|
when csr_misa_c => -- misa (r/-): ISA and extensions
|
when csr_misa_c => -- misa (r/-): ISA and extensions
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension
|
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
| Line 2273... |
Line 2165... |
when csr_mscratch_c => -- mscratch (r/w): machine scratch register
|
when csr_mscratch_c => -- mscratch (r/w): machine scratch register
|
csr.rdata <= csr.mscratch;
|
csr.rdata <= csr.mscratch;
|
when csr_mepc_c => -- mepc (r/w): machine exception program counter
|
when csr_mepc_c => -- mepc (r/w): machine exception program counter
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
when csr_mcause_c => -- mcause (r/w): machine trap cause
|
when csr_mcause_c => -- mcause (r/w): machine trap cause
|
csr.rdata(31) <= csr.mcause(csr.mcause'left);
|
csr.rdata(31) <= csr.mcause(5);
|
csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
|
csr.rdata(4 downto 0) <= csr.mcause(4 downto 0);
|
when csr_mtval_c => -- mtval (r/-): machine bad address or instruction
|
when csr_mtval_c => -- mtval (r/-): machine bad address or instruction
|
csr.rdata <= csr.mtval;
|
csr.rdata <= csr.mtval;
|
when csr_mip_c => -- mip (r/w): machine interrupt pending
|
when csr_mip_c => -- mip (r/w): machine interrupt pending
|
csr.rdata(03) <= trap_ctrl.irq_buf(irq_msw_irq_c);
|
csr.rdata(03) <= trap_ctrl.irq_buf(irq_msw_irq_c);
|
csr.rdata(07) <= trap_ctrl.irq_buf(irq_mtime_irq_c);
|
csr.rdata(07) <= trap_ctrl.irq_buf(irq_mtime_irq_c);
|
| Line 2522... |
Line 2414... |
|
|
-- Control and Status Registers - Counters ------------------------------------------------
|
-- Control and Status Registers - Counters ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_counters: process(rstn_i, clk_i)
|
csr_counters: process(rstn_i, clk_i)
|
begin
|
begin
|
-- Counter CSRs (each counter is split into two 32-bit counters - coupled via an MSB overflow FF)
|
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
csr.mcycle <= (others => def_rst_val_c);
|
csr.mcycle <= (others => def_rst_val_c);
|
csr.mcycle_ovfl <= (others => def_rst_val_c);
|
csr.mcycle_ovfl <= (others => def_rst_val_c);
|
csr.mcycleh <= (others => def_rst_val_c);
|
csr.mcycleh <= (others => def_rst_val_c);
|
csr.minstret <= (others => def_rst_val_c);
|
csr.minstret <= (others => def_rst_val_c);
|
| Line 2544... |
Line 2435... |
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
|
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
|
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
|
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
|
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0);
|
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0);
|
end if;
|
end if;
|
else
|
else
|
csr.mcycle_ovfl <= (others => '-');
|
csr.mcycle_ovfl <= (others => '0');
|
csr.mcycle <= (others => '-');
|
csr.mcycle <= (others => '0');
|
end if;
|
end if;
|
|
|
-- [m]cycleh --
|
-- [m]cycleh --
|
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
|
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
|
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
|
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
|
else -- automatic update
|
else -- automatic update
|
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mcycle_ovfl));
|
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mcycle_ovfl));
|
end if;
|
end if;
|
else
|
else
|
csr.mcycleh <= (others => '-');
|
csr.mcycleh <= (others => '0');
|
end if;
|
end if;
|
|
|
|
|
-- [m]instret --
|
-- [m]instret --
|
if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
| Line 2569... |
Line 2460... |
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
|
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
|
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
|
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
|
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0);
|
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0);
|
end if;
|
end if;
|
else
|
else
|
csr.minstret_ovfl <= (others => '-');
|
csr.minstret_ovfl <= (others => '0');
|
csr.minstret <= (others => '-');
|
csr.minstret <= (others => '0');
|
end if;
|
end if;
|
|
|
-- [m]instreth --
|
-- [m]instreth --
|
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
|
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
|
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
|
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
|
else -- automatic update
|
else -- automatic update
|
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.minstret_ovfl));
|
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.minstret_ovfl));
|
end if;
|
end if;
|
else
|
else
|
csr.minstreth <= (others => '-');
|
csr.minstreth <= (others => '0');
|
end if;
|
end if;
|
|
|
|
|
-- [machine] hardware performance monitors (counters) --
|
-- [machine] hardware performance monitors (counters) --
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
| Line 2597... |
Line 2488... |
csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.wdata(hpm_cnt_lo_width_c-1 downto 0);
|
csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.wdata(hpm_cnt_lo_width_c-1 downto 0);
|
elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
|
elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
|
csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter_nxt(i)(hpm_cnt_lo_width_c-1 downto 0);
|
csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter_nxt(i)(hpm_cnt_lo_width_c-1 downto 0);
|
end if;
|
end if;
|
else
|
else
|
csr.mhpmcounter_ovfl(i) <= (others => '-');
|
csr.mhpmcounter_ovfl(i) <= (others => '0');
|
csr.mhpmcounter(i) <= (others => '-');
|
csr.mhpmcounter(i) <= (others => '0');
|
end if;
|
end if;
|
|
|
-- [m]hpmcounter*h --
|
-- [m]hpmcounter*h --
|
if (hpm_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
|
if (hpm_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
|
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
|
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
|
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.wdata(hpm_cnt_hi_width_c-1 downto 0);
|
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.wdata(hpm_cnt_hi_width_c-1 downto 0);
|
else -- automatic update
|
else -- automatic update
|
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mhpmcounter_ovfl(i)));
|
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mhpmcounter_ovfl(i)));
|
end if;
|
end if;
|
else
|
else
|
csr.mhpmcounterh(i) <= (others => '-');
|
csr.mhpmcounterh(i) <= (others => '0');
|
end if;
|
end if;
|
|
|
end loop; -- i
|
end loop; -- i
|
|
|
end if;
|
end if;
|
| Line 2648... |
Line 2539... |
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
end process hpm_rd_dummy;
|
end process hpm_rd_dummy;
|
|
|
|
|
-- Hardware Performance Monitor - Counter Event Control -----------------------------------
|
-- Hardware Performance Monitor - Counter Event Control (Triggers) ------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
hpmcnt_ctrl: process(clk_i)
|
hpmcnt_ctrl: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- enable selected triggers by ANDing actual events and according CSR configuration bits --
|
-- enable selected triggers by ANDing actual events and according CSR configuration bits --
|
-- OR everything to see if counter should increment --
|
-- OR everything to see if counter should increment --
|
hpmcnt_trigger <= (others => '0'); -- default
|
hpmcnt_trigger <= (others => '0'); -- default
|
if (HPM_NUM_CNTS /= 0) then
|
if (HPM_NUM_CNTS /= 0) then
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
-- do not increment if CPU is in debug mode --
|
-- do not increment if CPU is in debug mode --
|
hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)) and (not debug_ctrl.running);
|
if (or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)) = '1') and (debug_ctrl.running = '0') then
|
|
hpmcnt_trigger(i) <= '1';
|
|
else
|
|
hpmcnt_trigger(i) <= '0';
|
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
end if;
|
end if;
|
end process hpmcnt_ctrl;
|
end process hpmcnt_ctrl;
|
|
|
|
hpm_triggers:
|
|
if (HPM_NUM_CNTS /= 0) generate
|
-- counter event trigger - RISC-V-specific --
|
-- counter event trigger - RISC-V-specific --
|
cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
|
cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
|
cnt_event(hpmcnt_event_never_c) <= '0'; -- "never"
|
cnt_event(hpmcnt_event_never_c) <= '0'; -- "never"
|
cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- (any) retired instruction
|
cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- (any) retired instruction
|
|
|
| Line 2686... |
Line 2583... |
cnt_event(hpmcnt_event_branch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
|
cnt_event(hpmcnt_event_branch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
|
cnt_event(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
|
cnt_event(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
|
|
|
cnt_event(hpmcnt_event_trap_c) <= '1' when (trap_ctrl.env_start_ack = '1') else '0'; -- entered trap
|
cnt_event(hpmcnt_event_trap_c) <= '1' when (trap_ctrl.env_start_ack = '1') else '0'; -- entered trap
|
cnt_event(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
|
cnt_event(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
|
|
end generate;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- CPU Debug Mode (Part of the On-Chip Debugger)
|
-- CPU Debug Mode (Part of the On-Chip Debugger)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Debug Control --------------------------------------------------------------------------
|
-- Debug Control --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
ocd_en:
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) generate
|
debug_control: process(rstn_i, clk_i)
|
debug_control: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
debug_ctrl.ext_halt_req <= '0';
|
debug_ctrl.ext_halt_req <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
|
|
|
-- external halt request (from Debug Module) --
|
-- external halt request (from Debug Module) --
|
debug_ctrl.ext_halt_req <= db_halt_req_i;
|
debug_ctrl.ext_halt_req <= db_halt_req_i;
|
|
|
-- state machine --
|
-- state machine --
|
case debug_ctrl.state is
|
case debug_ctrl.state is
|
| Line 2735... |
Line 2633... |
|
|
when others => -- undefined
|
when others => -- undefined
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
|
|
end case;
|
end case;
|
else -- debug mode NOT implemented
|
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
|
debug_ctrl.ext_halt_req <= '0';
|
|
end if;
|
|
end if;
|
end if;
|
end process debug_control;
|
end process debug_control;
|
|
end generate;
|
|
|
-- state decoding --
|
-- state decoding --
|
debug_ctrl.pending <= '1' when (debug_ctrl.state = DEBUG_PENDING) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
|
debug_ctrl.pending <= '1' when (debug_ctrl.state = DEBUG_PENDING) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
|
debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
|
debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
|
|
|
| Line 2780... |
Line 2675... |
-- Hardware Trigger Module (Part of the On-Chip Debugger)
|
-- Hardware Trigger Module (Part of the On-Chip Debugger)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- trigger to enter debug-mode: instruction address match (fire AFTER execution) --
|
-- trigger to enter debug-mode: instruction address match (fire AFTER execution) --
|
hw_trigger_fire <= '1' when (CPU_EXTENSION_RISCV_DEBUG = true) and (csr.tdata1_exe = '1') and
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hw_trigger_fire <= '1' when (CPU_EXTENSION_RISCV_DEBUG = true) and (csr.tdata1_exe = '1') and
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(csr.tdata2(data_width_c-1 downto 1) = execute_engine.pc(data_width_c-1 downto 1)) else '0';
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(csr.tdata2(data_width_c-1 downto 1) = execute_engine.pc(data_width_c-1 downto 1)) and
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(execute_engine.state = EXECUTE) else '0';
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|
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-- Match Control CSR (mcontrol @ tdata1) - Read-Back --------------------------------------
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-- Match Control CSR (mcontrol @ tdata1) - Read-Back --------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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csr.tdata1_rd(31 downto 28) <= "0010"; -- type: address(/data) match trigger
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csr.tdata1_rd(31 downto 28) <= "0010"; -- type: address(/data) match trigger
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