| Line 89... |
Line 89... |
signal div_opy : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_opy : std_ulogic_vector(data_width_c-1 downto 0);
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signal rs1_is_signed : std_ulogic;
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signal rs1_is_signed : std_ulogic;
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signal rs2_is_signed : std_ulogic;
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signal rs2_is_signed : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal out_en : std_ulogic;
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signal out_en : std_ulogic;
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signal rs2_zero : std_ulogic;
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-- divider core --
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-- divider core --
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signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
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signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
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signal quotient : std_ulogic_vector(data_width_c-1 downto 0);
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signal quotient : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sub : std_ulogic_vector(data_width_c downto 0);
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signal div_sub : std_ulogic_vector(data_width_c downto 0);
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| Line 150... |
Line 151... |
end if;
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end if;
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when DIV_PREPROCESS =>
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when DIV_PREPROCESS =>
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-- check relevant input signs for result sign compensation --
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-- check relevant input signs for result sign compensation --
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if (cp_op = cp_op_div_c) then -- signed div operation
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if (cp_op = cp_op_div_c) then -- signed div operation
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div_res_corr <= (rs1_i(rs1_i'left) xor rs2_i(rs2_i'left)) and or_reduce_f(rs2_i); -- different signs AND rs2 not zero
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div_res_corr <= (rs1_i(rs1_i'left) xor rs2_i(rs2_i'left)) and (not rs2_zero); -- different signs AND rs2 not zero
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elsif (cp_op = cp_op_rem_c) then -- signed rem operation
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elsif (cp_op = cp_op_rem_c) then -- signed rem operation
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div_res_corr <= rs1_i(rs1_i'left);
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div_res_corr <= rs1_i(rs1_i'left);
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else
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else
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div_res_corr <= '0';
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div_res_corr <= '0';
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end if;
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end if;
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Line 182... |
state <= IDLE;
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state <= IDLE;
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end case;
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end case;
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end if;
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end if;
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end process coprocessor_ctrl;
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end process coprocessor_ctrl;
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-- rs2 zero? --
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rs2_zero <= '1' when (or_reduce_f(rs2_i) = '0') else '0';
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-- co-processor command --
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-- co-processor command --
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cp_op <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
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cp_op <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
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-- operation: 0=mul, 1=div --
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-- operation: 0=mul, 1=div --
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operation <= '1' when (cp_op(2) = '1') else '0';
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operation <= '1' when (cp_op(2) = '1') else '0';
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