//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 alu source select module ////
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//// 8051 alu source select module ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Multiplexer wiht whitch we select data on alu sources ////
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//// Multiplexer wiht whitch we select data on alu sources ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 19th Jan 2017
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//// 1. Lint Error fix
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/06/03 17:13:57 simont
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// Revision 1.3 2003/06/03 17:13:57 simont
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// remove pc_r register.
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// remove pc_r register.
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//
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//
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// Revision 1.2 2003/05/06 09:41:35 simont
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// Revision 1.2 2003/05/06 09:41:35 simont
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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//
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//
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// Revision 1.1 2003/01/13 14:13:12 simont
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// Revision 1.1 2003/01/13 14:13:12 simont
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// initial import
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// initial import
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//
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//
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//
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//
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_alu_src_sel (clk, resetn, rd, sel1, sel2, sel3,
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module oc8051_alu_src_sel (clk, resetn, rd, sel1, sel2, sel3,
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acc, ram, pc, dptr,
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acc, ram, pc, dptr,
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op1, op2, op3,
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op1, op2, op3,
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src1, src2, src3);
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src1, src2, src3);
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input clk, resetn, rd, sel3;
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input clk, resetn, rd, sel3;
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input [1:0] sel2;
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input [1:0] sel2;
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input [2:0] sel1;
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input [2:0] sel1;
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input [7:0] acc, ram;
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input [7:0] acc, ram;
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input [15:0] dptr;
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input [15:0] dptr;
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input [15:0] pc;
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input [15:0] pc;
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input [7:0] op1, op2, op3;
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input [7:0] op1, op2, op3;
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output [7:0] src1, src2, src3;
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output [7:0] src1, src2, src3;
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reg [7:0] src1, src2, src3;
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reg [7:0] src1, src2, src3;
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reg [7:0] op1_r, op2_r, op3_r;
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reg [7:0] op1_r, op2_r, op3_r;
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///////
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///////
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//
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//
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// src1
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// src1
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//
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//
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///////
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///////
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always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
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always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
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begin
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begin
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case (sel1) /* synopsys full_case parallel_case */
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case (sel1) /* synopsys full_case parallel_case */
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`OC8051_AS1_RAM: src1 = ram;
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`OC8051_AS1_RAM: src1 = ram;
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`OC8051_AS1_ACC: src1 = acc;
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`OC8051_AS1_ACC: src1 = acc;
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`OC8051_AS1_OP1: src1 = op1_r;
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`OC8051_AS1_OP1: src1 = op1_r;
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`OC8051_AS1_OP2: src1 = op2_r;
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`OC8051_AS1_OP2: src1 = op2_r;
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`OC8051_AS1_OP3: src1 = op3_r;
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`OC8051_AS1_OP3: src1 = op3_r;
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`OC8051_AS1_PCH: src1 = pc[15:8];
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`OC8051_AS1_PCH: src1 = pc[15:8];
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`OC8051_AS1_PCL: src1 = pc[7:0];
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`OC8051_AS1_PCL: src1 = pc[7:0];
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// default: src1 = 8'h00;
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default: src1 = 8'h00;
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endcase
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endcase
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end
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end
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///////
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///////
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//
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//
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// src2
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// src2
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//
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//
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///////
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///////
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always @(sel2 or op2_r or acc or ram or op1_r)
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always @(sel2 or op2_r or acc or ram or op1_r)
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begin
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begin
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case (sel2) /* synopsys full_case parallel_case */
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case (sel2) /* synopsys full_case parallel_case */
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`OC8051_AS2_ACC: src2= acc;
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`OC8051_AS2_ACC: src2= acc;
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`OC8051_AS2_ZERO: src2= 8'h00;
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`OC8051_AS2_ZERO: src2= 8'h00;
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`OC8051_AS2_RAM: src2= ram;
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`OC8051_AS2_RAM: src2= ram;
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`OC8051_AS2_OP2: src2= op2_r;
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`OC8051_AS2_OP2: src2= op2_r;
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// default: src2= 8'h00;
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// default: src2= 8'h00;
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endcase
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endcase
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end
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end
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///////
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///////
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//
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//
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// src3
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// src3
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//
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//
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///////
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///////
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always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
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always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
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begin
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begin
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case (sel3) /* synopsys full_case parallel_case */
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case (sel3) /* synopsys full_case parallel_case */
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`OC8051_AS3_DP: src3= dptr[15:8];
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`OC8051_AS3_DP: src3= dptr[15:8];
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`OC8051_AS3_PC: src3= pc[15:8];
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`OC8051_AS3_PC: src3= pc[15:8];
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// default: src3= 16'h0;
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// default: src3= 16'h0;
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endcase
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endcase
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end
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end
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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op1_r <= #1 8'h00;
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op1_r <= 8'h00;
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op2_r <= #1 8'h00;
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op2_r <= 8'h00;
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op3_r <= #1 8'h00;
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op3_r <= 8'h00;
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end else begin
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end else begin
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op1_r <= #1 op1;
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op1_r <= op1;
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op2_r <= #1 op2;
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op2_r <= op2;
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op3_r <= #1 op3;
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op3_r <= op3;
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end
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end
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endmodule
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endmodule
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