//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 indirect address ////
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//// 8051 indirect address ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Contains ragister 0 and register 1. used for indirrect ////
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//// Contains ragister 0 and register 1. used for indirrect ////
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//// addressing. ////
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//// addressing. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 19th Jan 2017
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//// 1. Lint warning fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/05/05 15:46:37 simont
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// Revision 1.6 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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// add aditional alu destination to solve critical path.
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//
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//
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// Revision 1.5 2003/01/13 14:14:41 simont
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// Revision 1.5 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.4 2002/09/30 17:33:59 simont
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// Revision 1.4 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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module oc8051_indi_addr (clk, resetn, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
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module oc8051_indi_addr (clk, resetn, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
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//
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//
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input clk, // clock
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input clk, // clock
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resetn, // reset
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resetn, // reset
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wr, // write
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wr, // write
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sel, // select register
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sel, // select register
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wr_bit; // write bit addressable
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wr_bit; // write bit addressable
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input [1:0] bank; // select register bank
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input [1:0] bank; // select register bank
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input [7:0] data_in; // data input
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input [7:0] data_in; // data input
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input [7:0] wr_addr; // write address
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input [7:0] wr_addr; // write address
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output [7:0] ri_out;
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output [7:0] ri_out;
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//reg [7:0] buff [31:0];
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//reg [7:0] buff [31:0];
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reg wr_bit_r;
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reg wr_bit_r;
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reg [7:0] buff [0:7];
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reg [7:0] buff [0:7];
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//
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//
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//write to buffer
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//write to buffer
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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buff[3'b000] <= #1 8'h00;
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buff[3'b000] <= #1 8'h00;
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buff[3'b001] <= #1 8'h00;
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buff[3'b001] <= #1 8'h00;
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buff[3'b010] <= #1 8'h00;
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buff[3'b010] <= #1 8'h00;
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buff[3'b011] <= #1 8'h00;
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buff[3'b011] <= #1 8'h00;
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buff[3'b100] <= #1 8'h00;
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buff[3'b100] <= #1 8'h00;
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buff[3'b101] <= #1 8'h00;
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buff[3'b101] <= #1 8'h00;
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buff[3'b110] <= #1 8'h00;
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buff[3'b110] <= #1 8'h00;
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buff[3'b111] <= #1 8'h00;
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buff[3'b111] <= #1 8'h00;
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end else begin
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end else begin
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if ((wr) & !(wr_bit_r)) begin
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if ((wr) & !(wr_bit_r)) begin
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case (wr_addr) /* synopsys full_case parallel_case */
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case (wr_addr) /* synopsys full_case parallel_case */
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8'h00: buff[3'b000] <= #1 data_in;
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8'h00: buff[3'b000] <= #1 data_in;
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8'h01: buff[3'b001] <= #1 data_in;
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8'h01: buff[3'b001] <= #1 data_in;
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8'h08: buff[3'b010] <= #1 data_in;
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8'h08: buff[3'b010] <= #1 data_in;
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8'h09: buff[3'b011] <= #1 data_in;
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8'h09: buff[3'b011] <= #1 data_in;
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8'h10: buff[3'b100] <= #1 data_in;
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8'h10: buff[3'b100] <= #1 data_in;
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8'h11: buff[3'b101] <= #1 data_in;
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8'h11: buff[3'b101] <= #1 data_in;
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8'h18: buff[3'b110] <= #1 data_in;
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8'h18: buff[3'b110] <= #1 data_in;
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8'h19: buff[3'b111] <= #1 data_in;
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8'h19: buff[3'b111] <= #1 data_in;
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default : buff[3'b000] <= #1 data_in;
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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//
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//
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//read from buffer
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//read from buffer
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assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
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assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
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data_in : buff[{bank, sel}];
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data_in : buff[{bank, sel}];
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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wr_bit_r <= #1 1'b0;
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wr_bit_r <= #1 1'b0;
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end else begin
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end else begin
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wr_bit_r <= #1 wr_bit;
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wr_bit_r <= #1 wr_bit;
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end
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end
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endmodule
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endmodule
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