//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// multiply for 8051 Core ////
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//// multiply for 8051 Core ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implementation of multipication used in alu.v ////
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//// Implementation of multipication used in alu.v ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Marko Mlinar, markom@opencores.org ////
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//// - Marko Mlinar, markom@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/09/30 17:33:59 simont
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// Revision 1.8 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// ver: 2 markom
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// ver: 2 markom
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// changed to two cycle multiplication, to save resources and
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// changed to two cycle multiplication, to save resources and
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// increase speed
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// increase speed
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//
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//
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// ver: 3 markom
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// ver: 3 markom
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// changed to four cycle multiplication, to save resources and
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// changed to four cycle multiplication, to save resources and
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// increase speed
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// increase speed
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module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
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module oc8051_multiply (clk, resetn, enable, src1, src2, des1, des2, desOv);
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//
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//
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// this module is part of alu
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// this module is part of alu
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// clk (in)
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// clk (in)
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// rst (in)
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// resetn (in)
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// enable (in)
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// enable (in)
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// src1 (in) first operand
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// src1 (in) first operand
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// src2 (in) second operand
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// src2 (in) second operand
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// des1 (out) first result
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// des1 (out) first result
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// des2 (out) second result
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// des2 (out) second result
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// desOv (out) Overflow output
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// desOv (out) Overflow output
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//
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//
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input clk, rst, enable;
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input clk, resetn, enable;
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input [7:0] src1, src2;
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input [7:0] src1, src2;
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output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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// wires
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// wires
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wire [15:0] mul_result1, mul_result, shifted;
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wire [15:0] mul_result1, mul_result, shifted;
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// real registers
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// real registers
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reg [1:0] cycle;
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reg [1:0] cycle;
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reg [15:0] tmp_mul;
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reg [15:0] tmp_mul;
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assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
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assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
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: cycle == 2'h1 ? src2[5:4]
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: cycle == 2'h1 ? src2[5:4]
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: cycle == 2'h2 ? src2[3:2]
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: cycle == 2'h2 ? src2[3:2]
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: src2[1:0]);
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: src2[1:0]);
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assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
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assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
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assign mul_result = mul_result1 + shifted;
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assign mul_result = mul_result1 + shifted;
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assign des1 = mul_result[15:8];
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assign des1 = mul_result[15:8];
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assign des2 = mul_result[7:0];
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assign des2 = mul_result[7:0];
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assign desOv = | des1;
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assign desOv = | des1;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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cycle <= #1 2'b0;
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cycle <= #1 2'b0;
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tmp_mul <= #1 16'b0;
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tmp_mul <= #1 16'b0;
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end else begin
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end else begin
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if (enable) cycle <= #1 cycle + 2'b1;
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if (enable) cycle <= #1 cycle + 2'b1;
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tmp_mul <= #1 mul_result;
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tmp_mul <= #1 mul_result;
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end
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end
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end
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end
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endmodule
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endmodule
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