//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 port output ////
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//// 8051 port output ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 8051 special function registers: port 0:3 - output ////
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//// 8051 special function registers: port 0:3 - output ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, simont@opencores.org ////
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//// - Dinesh Annayya, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/04/10 12:43:19 simont
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// Revision 1.9 2003/04/10 12:43:19 simont
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// defines for pherypherals added
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// defines for pherypherals added
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//
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//
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// Revision 1.8 2003/04/07 14:58:02 simont
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// Revision 1.8 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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//
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//
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// Revision 1.7 2003/01/13 14:14:41 simont
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// Revision 1.7 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.6 2002/09/30 17:33:59 simont
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// Revision 1.6 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_ports (clk,
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module oc8051_ports (clk,
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rst,
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resetn,
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bit_in,
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bit_in,
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data_in,
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data_in,
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wr,
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wr,
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wr_bit,
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wr_bit,
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wr_addr,
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wr_addr,
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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p0_out,
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p0_out,
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p0_in,
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p0_in,
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p0_data,
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p0_data,
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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p1_out,
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p1_out,
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p1_in,
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p1_in,
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p1_data,
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p1_data,
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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p2_out,
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p2_out,
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p2_in,
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p2_in,
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p2_data,
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p2_data,
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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p3_out,
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p3_out,
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p3_in,
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p3_in,
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p3_data,
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p3_data,
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`endif
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`endif
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rmw);
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rmw);
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input clk, //clock
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input clk, //clock
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rst, //reset
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resetn, //reset
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wr, //write [oc8051_decoder.wr -r]
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wr, //write [oc8051_decoder.wr -r]
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wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
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wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
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bit_in, //bit input [oc8051_alu.desCy]
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bit_in, //bit input [oc8051_alu.desCy]
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rmw; //read modify write feature [oc8051_decoder.rmw]
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rmw; //read modify write feature [oc8051_decoder.rmw]
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input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]
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input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]
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data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]
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data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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input [7:0] p0_in;
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input [7:0] p0_in;
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output [7:0] p0_out,
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output [7:0] p0_out,
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p0_data;
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p0_data;
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reg [7:0] p0_out;
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reg [7:0] p0_out;
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assign p0_data = rmw ? p0_out : p0_in;
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assign p0_data = rmw ? p0_out : p0_in;
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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input [7:0] p1_in;
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input [7:0] p1_in;
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output [7:0] p1_out,
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output [7:0] p1_out,
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p1_data;
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p1_data;
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reg [7:0] p1_out;
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reg [7:0] p1_out;
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assign p1_data = rmw ? p1_out : p1_in;
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assign p1_data = rmw ? p1_out : p1_in;
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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input [7:0] p2_in;
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input [7:0] p2_in;
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output [7:0] p2_out,
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output [7:0] p2_out,
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p2_data;
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p2_data;
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reg [7:0] p2_out;
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reg [7:0] p2_out;
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assign p2_data = rmw ? p2_out : p2_in;
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assign p2_data = rmw ? p2_out : p2_in;
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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input [7:0] p3_in;
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input [7:0] p3_in;
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output [7:0] p3_out,
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output [7:0] p3_out,
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p3_data;
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p3_data;
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reg [7:0] p3_out;
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reg [7:0] p3_out;
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assign p3_data = rmw ? p3_out : p3_in;
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assign p3_data = rmw ? p3_out : p3_in;
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`endif
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`endif
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//
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//
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// case of writing to port
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// case of writing to port
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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p0_out <= #1 `OC8051_RST_P0;
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p0_out <= #1 `OC8051_RST_P0;
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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p1_out <= #1 `OC8051_RST_P1;
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p1_out <= #1 `OC8051_RST_P1;
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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p2_out <= #1 `OC8051_RST_P2;
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p2_out <= #1 `OC8051_RST_P2;
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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p3_out <= #1 `OC8051_RST_P3;
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p3_out <= #1 `OC8051_RST_P3;
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`endif
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`endif
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end else if (wr) begin
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end else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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case (wr_addr) /* synopsys full_case parallel_case */
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case (wr_addr) /* synopsys full_case parallel_case */
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//
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//
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// bytaddresable
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// bytaddresable
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_P0: begin p0_out <= #1 data_in;
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`OC8051_SFR_P0: begin p0_out <= #1 data_in;
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end
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end
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`endif
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`endif
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endcase
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endcase
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end else begin
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end else begin
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case (wr_addr[7:3]) /* synopsys full_case parallel_case */
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case (wr_addr[7:3]) /* synopsys full_case parallel_case */
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//
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//
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// bit addressable
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// bit addressable
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`endif
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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