//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 internal ram ////
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//// 8051 internal ram ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 256 bytes two port ram ////
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//// 256 bytes two port ram ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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//
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//
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// two port ram
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// two port ram
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//
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//
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module oc8051_ram_256x8_two_bist (
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module oc8051_ram_256x8_two_bist (
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clk,
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clk,
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resetn,
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resetn,
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rd_addr,
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rd_addr,
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rd_data,
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rd_data,
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rd_en,
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rd_en,
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wr_addr,
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wr_addr,
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wr_data,
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wr_data,
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wr_en,
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wr_en,
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wr
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wr
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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,
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,
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scanb_rst,
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scanb_rst,
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scanb_clk,
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scanb_clk,
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scanb_si,
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scanb_si,
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scanb_so,
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scanb_so,
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scanb_en
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scanb_en
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`endif
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`endif
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);
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);
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input clk,
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input clk,
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wr,
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wr,
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resetn,
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resetn,
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rd_en,
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rd_en,
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wr_en;
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wr_en;
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input [7:0] wr_data;
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input [7:0] wr_data;
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input [7:0] rd_addr,
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input [7:0] rd_addr,
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wr_addr;
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wr_addr;
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output [7:0] rd_data;
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output [7:0] rd_data;
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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input scanb_rst;
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input scanb_rst;
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input scanb_clk;
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input scanb_clk;
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input scanb_si;
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input scanb_si;
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output scanb_so;
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output scanb_so;
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input scanb_en;
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input scanb_en;
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`endif
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`endif
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`ifdef OC8051_RAM_XILINX
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`ifdef OC8051_RAM_XILINX
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xilinx_ram_dp u_ram(
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xilinx_ram_dp u_ram(
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// read port
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// read port
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.CLKA(clk),
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.CLKA(clk),
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.RSTA(resetn),
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.RSTA(resetn),
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.ENA(rd_en),
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.ENA(rd_en),
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.ADDRA(rd_addr),
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.ADDRA(rd_addr),
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.DIA(8'h00),
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.DIA(8'h00),
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.WEA(1'b0),
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.WEA(1'b0),
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.DOA(rd_data),
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.DOA(rd_data),
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|
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// write port
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// write port
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.CLKB(clk),
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.CLKB(clk),
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.RSTB(resetn),
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.RSTB(resetn),
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.ENB(wr_en),
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.ENB(wr_en),
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.ADDRB(wr_addr),
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.ADDRB(wr_addr),
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.DIB(wr_data),
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.DIB(wr_data),
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.WEB(wr),
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.WEB(wr),
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.DOB()
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.DOB()
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);
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);
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defparam
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defparam
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xilinx_ram.dwidth = 8,
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xilinx_ram.dwidth = 8,
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xilinx_ram.awidth = 8;
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xilinx_ram.awidth = 8;
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`elsif OC8051_RAM_VIRTUALSILICON
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`elsif OC8051_RAM_VIRTUALSILICON
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`elsif OC8051_RAM_ACTEL
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`elsif OC8051_RAM_ACTEL
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oc8051_actel_ram_256x8 u_ram(
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oc8051_actel_ram_256x8 u_ram(
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.RWCLK ( clk ),
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.RWCLK ( clk ),
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.RESET ( resetn ),
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.RESET ( resetn ),
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.REN ( rd_en ),
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.REN ( rd_en ),
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.RADDR ( rd_addr ),
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.RADDR ( rd_addr ),
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.RD ( rd_data ),
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.RD ( rd_data ),
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|
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.WEN ( wr ),
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.WEN ( wr ),
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.WADDR ( wr_addr ),
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.WADDR ( wr_addr ),
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.WD ( wr_data )
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.WD ( wr_data )
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);
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);
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`elsif OC8051_RAM_GENERIC
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`elsif OC8051_RAM_GENERIC
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generic_dpram #(8, 8) u_ram(
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generic_dpram #(8, 8) u_ram(
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.rclk ( clk ),
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.rclk ( clk ),
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.rresetn( resetn ),
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.rresetn( resetn ),
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.rce ( rd_en ),
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.rce ( rd_en ),
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.oe ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( rd_addr ),
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.raddr ( rd_addr ),
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.do ( rd_data ),
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.do ( rd_data ),
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|
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.wclk ( clk ),
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.wclk ( clk ),
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.wresetn ( resetn ),
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.wresetn ( resetn ),
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.wce ( wr_en ),
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.wce ( wr_en ),
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.we ( wr ),
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.we ( wr ),
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.waddr ( wr_addr ),
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.waddr ( wr_addr ),
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.di ( wr_data )
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.di ( wr_data )
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);
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);
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`else
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`else
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reg [7:0] rd_data;
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reg [7:0] rd_data;
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//
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//
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// buffer
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// buffer
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reg [7:0] buff [0:256];
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reg [7:0] buff [0:256];
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//
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//
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// writing to ram
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// writing to ram
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (wr)
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if (wr)
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buff[wr_addr] <= #1 wr_data;
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buff[wr_addr] <= wr_data;
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end
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end
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//
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//
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// reading from ram
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// reading from ram
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0)
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if (resetn == 1'b0)
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rd_data <= #1 8'h0;
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rd_data <= 8'h0;
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else if ((wr_addr==rd_addr) & wr & rd_en)
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else if ((wr_addr==rd_addr) & wr & rd_en)
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rd_data <= #1 wr_data;
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rd_data <= wr_data;
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else if (rd_en)
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else if (rd_en)
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rd_data <= #1 buff[rd_addr];
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rd_data <= buff[rd_addr];
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end
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end
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`endif //OC8051_RAM_XILINX
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`endif //OC8051_RAM_XILINX
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endmodule
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endmodule
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