//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 stack pointer ////
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//// 8051 stack pointer ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 8051 special function register: stack pointer. ////
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//// 8051 special function register: stack pointer. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 6th Jan 2017
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//// v0.1 - Dinesh A, 6th Jan 2017
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//// 1. pc_next logic added
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//// 1. pc_next logic added
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/01/13 14:14:41 simont
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// Revision 1.5 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.4 2002/11/05 17:23:54 simont
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// Revision 1.4 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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//
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//
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// Revision 1.3 2002/09/30 17:33:59 simont
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// Revision 1.3 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_sp (
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module oc8051_sp (
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// General I/F
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// General I/F
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clk,
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clk,
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resetn,
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resetn,
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ram_rd_sel,
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ram_rd_sel,
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ram_wr_sel,
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ram_wr_sel,
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// SP Reg Write I/F
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// SP Reg Write I/F
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wr_addr,
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wr_addr,
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wr,
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wr,
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wr_bit,
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wr_bit,
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data_in,
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data_in,
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sp_out,
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sp_out,
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sp_w);
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sp_w);
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input clk, resetn, wr, wr_bit;
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input clk, resetn, wr, wr_bit;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [7:0] data_in, wr_addr;
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input [7:0] data_in, wr_addr;
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output [7:0] sp_out, sp_w;
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output [7:0] sp_out, sp_w;
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reg [7:0] sp_out, sp_w;
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reg [7:0] sp_out, sp_w;
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reg pop;
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reg pop;
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wire write;
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wire write;
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wire [7:0] sp_t;
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wire [7:0] sp_t;
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|
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reg [7:0] sp;
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reg [7:0] sp;
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assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
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assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
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assign sp_t= write ? data_in : sp;
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assign sp_t= write ? data_in : sp;
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0)
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if (resetn == 1'b0)
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sp <= #1 `OC8051_RST_SP;
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sp <= `OC8051_RST_SP;
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else if (write)
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else if (write)
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sp <= #1 data_in;
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sp <= data_in;
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else
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else
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sp <= #1 sp_out;
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sp <= sp_out;
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end
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end
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always @(sp or ram_wr_sel)
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always @(sp or ram_wr_sel)
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begin
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begin
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//
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//
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// push
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// push
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if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
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if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
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else sp_w = sp;
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else sp_w = sp;
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end
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end
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|
always @(sp_t or ram_wr_sel or pop or write)
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always @(sp_t or ram_wr_sel or pop or write)
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begin
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begin
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//
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//
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// push
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// push
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if (write) sp_out = sp_t;
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if (write) sp_out = sp_t;
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else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
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else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
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else sp_out = sp_t - {7'b0, pop};
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else sp_out = sp_t - {7'b0, pop};
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|
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end
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end
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|
|
|
always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
pop <= #1 1'b0;
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pop <= 1'b0;
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else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
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else if (ram_rd_sel==`OC8051_RRS_SP) pop <= 1'b1;
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else pop <= #1 1'b0;
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else pop <= 1'b0;
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end
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end
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endmodule
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endmodule
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