//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 wishbone interface to instruction rom ////
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//// 8051 wishbone interface to instruction rom ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/05/05 10:34:27 simont
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// Revision 1.5 2003/05/05 10:34:27 simont
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// registering outputs.
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// registering outputs.
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//
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//
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// Revision 1.4 2003/04/16 10:02:45 simont
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// Revision 1.4 2003/04/16 10:02:45 simont
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// fix bug (cyc_o and stb_o)
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// fix bug (cyc_o and stb_o)
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//
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//
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// Revision 1.3 2003/04/03 19:19:02 simont
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// Revision 1.3 2003/04/03 19:19:02 simont
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// change adr_i and adr_o length.
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// change adr_i and adr_o length.
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//
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//
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// Revision 1.2 2003/01/13 14:14:41 simont
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// Revision 1.2 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.1 2002/10/28 16:42:08 simont
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// Revision 1.1 2002/10/28 16:42:08 simont
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// initial import
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// initial import
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//
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//
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//
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//
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//
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//
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module oc8051_wb_iinterface(resetn, clk,
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module oc8051_wb_iinterface(resetn, clk,
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_o, dat_i, cyc_o, stb_o, ack_i
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adr_o, dat_i, cyc_o, stb_o, ack_i
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);
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);
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//
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//
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// resetn (in) reset - pin
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// resetn (in) reset - pin
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// clk (in) clock - pini
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// clk (in) clock - pini
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input resetn, clk;
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input resetn, clk;
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//
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//
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// interface to oc8051 cpu
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// interface to oc8051 cpu
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//
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//
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// adr_i (in) address
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// adr_i (in) address
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// dat_o (out) data output
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// dat_o (out) data output
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// stb_i (in) strobe
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// stb_i (in) strobe
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// ack_o (out) acknowledge
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// ack_o (out) acknowledge
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// cyc_i (in) cycle
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// cyc_i (in) cycle
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input stb_i,
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input stb_i,
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cyc_i;
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cyc_i;
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input [15:0] adr_i;
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input [15:0] adr_i;
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output ack_o;
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output ack_o;
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output [31:0] dat_o;
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output [31:0] dat_o;
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//
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//
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// interface to instruction rom
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// interface to instruction rom
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//
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//
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// adr_o (out) address
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// adr_o (out) address
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// dat_i (in) data input
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// dat_i (in) data input
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// stb_o (out) strobe
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// stb_o (out) strobe
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// ack_i (in) acknowledge
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// ack_i (in) acknowledge
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// cyc_o (out) cycle
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// cyc_o (out) cycle
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input ack_i;
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input ack_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output stb_o,
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output stb_o,
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cyc_o;
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cyc_o;
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output [15:0] adr_o;
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output [15:0] adr_o;
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//
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//
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// internal bufers and wires
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// internal bufers and wires
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//
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//
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reg [15:0] adr_o;
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reg [15:0] adr_o;
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reg stb_o;
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reg stb_o;
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assign ack_o = ack_i;
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assign ack_o = ack_i;
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assign dat_o = dat_i;
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assign dat_o = dat_i;
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//assign stb_o = stb_i || ack_i;
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//assign stb_o = stb_i || ack_i;
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assign cyc_o = stb_o;
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assign cyc_o = stb_o;
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//assign adr_o = ack_i ? adr : adr_i;
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//assign adr_o = ack_i ? adr : adr_i;
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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stb_o <= #1 1'b0;
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stb_o <= 1'b0;
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adr_o <= #1 16'h0000;
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adr_o <= 16'h0000;
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end else if (ack_i) begin
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end else if (ack_i) begin
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stb_o <= #1 stb_i;
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stb_o <= stb_i;
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adr_o <= #1 adr_i;
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adr_o <= adr_i;
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end else if (!stb_o & stb_i) begin
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end else if (!stb_o & stb_i) begin
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stb_o <= #1 1'b1;
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stb_o <= 1'b1;
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adr_o <= #1 adr_i;
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adr_o <= adr_i;
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end
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end
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endmodule
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endmodule
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