//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS 8051 cores clockgen Module ////
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//// OMS 8051 cores clockgen Module ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//// Revision : Nov 26, 2016 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module clkgen (
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module clkgen (
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reset_n ,
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reset_n ,
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fastsim_mode ,
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fastsim_mode ,
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mastermode ,
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mastermode ,
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xtal_clk ,
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xtal_clk ,
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clkout ,
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clkout ,
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gen_resetn ,
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gen_resetn ,
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risc_reset ,
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risc_resetn ,
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app_clk ,
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app_clk ,
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uart_ref_clk
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uart_ref_clk
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);
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);
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input reset_n ; // Async reset signal
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input reset_n ; // Async reset signal
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input fastsim_mode ; // fast sim mode = 1
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input fastsim_mode ; // fast sim mode = 1
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input mastermode ; // 1 : Risc master mode
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input mastermode ; // 1 : Risc master mode
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input xtal_clk ; // Xtal clock-25Mhx
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input xtal_clk ; // Xtal clock-25Mhx
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output clkout ; // clock output, 250Mhz
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output clkout ; // clock output, 250Mhz
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output gen_resetn ; // internally generated reset
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output gen_resetn ; // internally generated reset
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output risc_reset ; // internally generated reset
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output risc_resetn ; // internally generated reset
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output app_clk ; // application clock
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output app_clk ; // application clock
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output uart_ref_clk ; // uart 16x Ref clock
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output uart_ref_clk ; // uart 16x Ref clock
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wire hard_reset_st ;
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wire hard_reset_st ;
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wire configure_st ;
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wire configure_st ;
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wire wait_pll_st ;
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wire wait_pll_st ;
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wire run_st ;
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wire run_st ;
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wire slave_run_st ;
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wire slave_run_st ;
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reg pll_done ;
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reg pll_done ;
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reg [11:0] pll_count ;
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reg [11:0] pll_count ;
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reg [2:0] clkgen_ps ;
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reg [2:0] clkgen_ps ;
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reg gen_resetn ; // internally generated reset
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reg gen_resetn ; // internally generated reset
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reg risc_reset ; // internally generated reset
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reg risc_resetn ; // internally generated reset
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assign clkout = app_clk;
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assign clkout = app_clk;
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wire pllout;
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wire pllout;
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/***********************************************
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/***********************************************
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Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
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Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
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*********************************************************/
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*********************************************************/
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/*******************
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/*******************
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altera_stargate_pll u_pll (
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altera_stargate_pll u_pll (
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. areset (!reset_n ),
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. areset (!reset_n ),
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. inclk0 (xtal_clk),
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. inclk0 (xtal_clk),
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. c0 (pllout),
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. c0 (pllout),
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. locked ()
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. locked ()
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);
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);
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*************************/
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*************************/
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assign pllout = xtal_clk;
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assign pllout = xtal_clk;
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//---------------------------------------------
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//---------------------------------------------
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//
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//
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// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
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// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
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//--------------------------------------------
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//--------------------------------------------
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always @(posedge xtal_clk or negedge reset_n)
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always @(posedge xtal_clk or negedge reset_n)
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begin // {
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begin // {
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if (!reset_n)
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if (!reset_n)
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begin // {
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begin // {
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pll_count <= 12'h9C4;
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pll_count <= 12'h9C4;
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end // }
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end // }
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else if (configure_st)
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else if (configure_st)
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begin // {
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begin // {
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pll_count <= (fastsim_mode) ? 12'h040 : 12'h9C4;
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pll_count <= (fastsim_mode) ? 12'h040 : 12'h9C4;
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end // }
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end // }
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else if (wait_pll_st)
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else if (wait_pll_st)
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begin // {
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begin // {
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pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);
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pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);
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end // }
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end // }
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end // }
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end // }
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/************************************************
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/************************************************
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PLL Timer Counter
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PLL Timer Counter
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************************************************/
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************************************************/
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always @(posedge xtal_clk or negedge reset_n)
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always @(posedge xtal_clk or negedge reset_n)
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begin
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begin
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if (!reset_n)
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if (!reset_n)
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pll_done <= 0;
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pll_done <= 0;
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else if (pll_count == 16'h0)
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else if (pll_count == 16'h0)
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pll_done <= 1;
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pll_done <= 1;
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else if (configure_st)
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else if (configure_st)
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pll_done <= 0;
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pll_done <= 0;
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end
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end
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/************************************************
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/************************************************
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internally generated reset
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internally generated reset
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************************************************/
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************************************************/
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always @(posedge xtal_clk or negedge reset_n )
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always @(posedge xtal_clk or negedge reset_n )
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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gen_resetn <= 0;
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gen_resetn <= 0;
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risc_reset <= 1;
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risc_resetn <= 0;
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end else if(run_st ) begin
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end else if(run_st ) begin
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gen_resetn <= 1;
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gen_resetn <= 1;
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risc_reset <= 0;
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risc_resetn <= 1;
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end else if(slave_run_st ) begin
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end else if(slave_run_st ) begin
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gen_resetn <= 1;
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gen_resetn <= 1;
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risc_reset <= 1; // Keet Risc in Reset
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risc_resetn <= 0; // Keet Risc in Reset
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end else begin
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end else begin
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gen_resetn <= 0;
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gen_resetn <= 0;
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risc_reset <= 1;
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risc_resetn <= 0;
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end
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end
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end
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end
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/****************************************
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/****************************************
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Reset State Machine
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Reset State Machine
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****************************************/
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****************************************/
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/*****************************************
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/*****************************************
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Define Clock Gen stat machine state
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Define Clock Gen stat machine state
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*****************************************/
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*****************************************/
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`define HARD_RESET 3'b000
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`define HARD_RESET 3'b000
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`define CONFIGURE 3'b001
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`define CONFIGURE 3'b001
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`define WAIT_PLL 3'b010
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`define WAIT_PLL 3'b010
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`define RUN 3'b011
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`define RUN 3'b011
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`define SLAVE_RUN 3'b100
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`define SLAVE_RUN 3'b100
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assign hard_reset_st = (clkgen_ps == `HARD_RESET);
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assign hard_reset_st = (clkgen_ps == `HARD_RESET);
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assign configure_st = (clkgen_ps == `CONFIGURE);
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assign configure_st = (clkgen_ps == `CONFIGURE);
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assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
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assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
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assign run_st = (clkgen_ps == `RUN);
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assign run_st = (clkgen_ps == `RUN);
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assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
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assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
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always @(posedge xtal_clk or negedge reset_n)
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always @(posedge xtal_clk or negedge reset_n)
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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clkgen_ps <= `HARD_RESET;
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clkgen_ps <= `HARD_RESET;
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end
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end
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else begin
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else begin
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case (clkgen_ps)
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case (clkgen_ps)
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`HARD_RESET:
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`HARD_RESET:
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clkgen_ps <= `CONFIGURE;
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clkgen_ps <= `CONFIGURE;
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`CONFIGURE:
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`CONFIGURE:
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clkgen_ps <= `WAIT_PLL;
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clkgen_ps <= `WAIT_PLL;
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`WAIT_PLL:
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`WAIT_PLL:
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if (pll_done) begin
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if (pll_done) begin
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if ( mastermode )
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if ( mastermode )
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clkgen_ps <= `RUN;
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clkgen_ps <= `RUN;
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else
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else
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clkgen_ps <= `SLAVE_RUN;
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clkgen_ps <= `SLAVE_RUN;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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//----------------------------------
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//----------------------------------
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// Generate Application clock 125Mhz
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// Generate Application clock 125Mhz
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//----------------------------------
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//----------------------------------
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clk_ctl #(1) u_appclk (
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clk_ctl #(1) u_appclk (
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// Outputs
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// Outputs
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.clk_o (app_clk),
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.clk_o (app_clk),
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// Inputs
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// Inputs
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.mclk (pllout),
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.mclk (pllout),
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.reset_n (gen_resetn),
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.reset_n (gen_resetn),
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.clk_div_ratio (2'b00)
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.clk_div_ratio (2'b00)
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);
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);
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//----------------------------------
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//----------------------------------
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// Generate Uart Ref Clock clock 50Mhz
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// Generate Uart Ref Clock clock 50Mhz
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// 200Mhz/(2+0) = 50Mhz
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// 200Mhz/(2+0) = 50Mhz
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// 250Mhz/(2+3) = 50Mhz
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// 250Mhz/(2+3) = 50Mhz
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//----------------------------------
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//----------------------------------
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clk_ctl #(2) u_uart_clk (
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clk_ctl #(2) u_uart_clk (
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// Outputs
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// Outputs
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.clk_o (uart_ref_clk),
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.clk_o (uart_ref_clk),
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// Inputs
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// Inputs
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.mclk (pllout ),
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.mclk (pllout ),
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.reset_n (gen_resetn ),
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.reset_n (gen_resetn ),
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.clk_div_ratio (3'b000 )
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.clk_div_ratio (3'b000 )
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);
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);
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endmodule
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endmodule
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