//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS8051 I2C Master byte-controller Module ////
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//// OMS8051 I2C Master byte-controller Module ////
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//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
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//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// -Richard Herveille , richard@asics.ws, www.asics.ws ////
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//// -Richard Herveille , richard@asics.ws, www.asics.ws ////
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//// -Dinesh Annayya, dinesha@opencores.org ////
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//// -Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Jan 6, 2017 ////
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//// Revision : Jan 6, 2017 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// v0.0 - Dinesh A, 6th Jan 2017
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//// v0.0 - Dinesh A, 6th Jan 2017
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// 1. Initail version picked from
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//// 1. Initail version picked from
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// http://www.opencores.org/projects/i2c/
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//// http://www.opencores.org/projects/i2c/
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// 2. renaming of reset signal to aresetn and sresetn
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//// 2. renaming of reset signal to aresetn and sresetn
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//
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//// v0.1 - Dinesh.A, 19th Jan 2017
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//// 1. Lint Error fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "i2cm_defines.v"
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`include "i2cm_defines.v"
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module i2cm_byte_ctrl (
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module i2cm_byte_ctrl (
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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input clk, // master clock
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input clk, // master clock
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input sresetn, // synchronous active high reset
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input sresetn, // synchronous active high reset
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input aresetn, // asynchronous active low reset
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input aresetn, // asynchronous active low reset
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input ena, // core enable signal
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input ena, // core enable signal
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|
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input [15:0] clk_cnt, // 4x SCL
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input [15:0] clk_cnt, // 4x SCL
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|
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// control inputs
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// control inputs
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input start,
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input start,
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input stop,
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input stop,
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input read,
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input read,
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input write,
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input write,
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input ack_in,
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input ack_in,
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input [7:0] din,
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input [7:0] din,
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|
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// status outputs
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// status outputs
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output reg cmd_ack,
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output reg cmd_ack,
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output reg ack_out,
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output reg ack_out,
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output i2c_busy,
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output i2c_busy,
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output i2c_al,
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output i2c_al,
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output [7:0] dout,
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output [7:0] dout,
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|
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// I2C signals
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// I2C signals
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input scl_i,
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input scl_i,
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output scl_o,
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output scl_o,
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output scl_oen,
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output scl_oen,
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input sda_i,
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input sda_i,
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output sda_o,
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output sda_o,
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output sda_oen
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output sda_oen
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|
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);
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);
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//
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//
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// Variable declarations
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// Variable declarations
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//
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//
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// statemachine
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// statemachine
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parameter [4:0] ST_IDLE = 5'b0_0000;
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parameter [4:0] ST_IDLE = 5'b0_0000;
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parameter [4:0] ST_START = 5'b0_0001;
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parameter [4:0] ST_START = 5'b0_0001;
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parameter [4:0] ST_READ = 5'b0_0010;
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parameter [4:0] ST_READ = 5'b0_0010;
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parameter [4:0] ST_WRITE = 5'b0_0100;
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parameter [4:0] ST_WRITE = 5'b0_0100;
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parameter [4:0] ST_ACK = 5'b0_1000;
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parameter [4:0] ST_ACK = 5'b0_1000;
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parameter [4:0] ST_STOP = 5'b1_0000;
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parameter [4:0] ST_STOP = 5'b1_0000;
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|
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// signals for bit_controller
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// signals for bit_controller
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reg [3:0] core_cmd;
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reg [3:0] core_cmd;
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reg core_txd;
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reg core_txd;
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wire core_ack, core_rxd;
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wire core_ack, core_rxd;
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|
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// signals for shift register
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// signals for shift register
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reg [7:0] sr; //8bit shift register
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reg [7:0] sr; //8bit shift register
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reg shift, ld;
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reg shift, ld;
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|
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// signals for state machine
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// signals for state machine
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wire go;
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wire go;
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reg [2:0] dcnt;
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reg [2:0] dcnt;
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wire cnt_done;
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wire cnt_done;
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//
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//
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// Module body
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// Module body
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//
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//
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// hookup bit_controller
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// hookup bit_controller
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i2cm_bit_ctrl u_bit_ctrl (
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i2cm_bit_ctrl u_bit_ctrl (
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.clk ( clk ),
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.clk ( clk ),
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.sresetn ( sresetn ),
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.sresetn ( sresetn ),
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.aresetn ( aresetn ),
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.aresetn ( aresetn ),
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.ena ( ena ),
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.ena ( ena ),
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.clk_cnt ( clk_cnt ),
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.clk_cnt ( clk_cnt ),
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.cmd ( core_cmd ),
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.cmd ( core_cmd ),
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.cmd_ack ( core_ack ),
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.cmd_ack ( core_ack ),
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.busy ( i2c_busy ),
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.busy ( i2c_busy ),
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.al ( i2c_al ),
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.al ( i2c_al ),
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.din ( core_txd ),
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.din ( core_txd ),
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.dout ( core_rxd ),
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.dout ( core_rxd ),
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.scl_i ( scl_i ),
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.scl_i ( scl_i ),
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.scl_o ( scl_o ),
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.scl_o ( scl_o ),
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.scl_oen ( scl_oen ),
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.scl_oen ( scl_oen ),
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.sda_i ( sda_i ),
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.sda_i ( sda_i ),
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.sda_o ( sda_o ),
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.sda_o ( sda_o ),
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.sda_oen ( sda_oen )
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.sda_oen ( sda_oen )
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);
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);
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// generate go-signal
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// generate go-signal
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assign go = (read | write | stop) & ~cmd_ack;
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assign go = (read | write | stop) & ~cmd_ack;
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// assign dout output to shift-register
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// assign dout output to shift-register
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assign dout = sr;
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assign dout = sr;
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// generate shift register
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// generate shift register
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always @(posedge clk or negedge aresetn)
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always @(posedge clk or negedge aresetn)
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if (!aresetn)
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if (!aresetn)
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sr <= #1 8'h0;
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sr <= 8'h0;
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else if (!sresetn)
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else if (!sresetn)
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sr <= #1 8'h0;
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sr <= 8'h0;
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else if (ld)
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else if (ld)
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sr <= #1 din;
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sr <= din;
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else if (shift)
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else if (shift)
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sr <= #1 {sr[6:0], core_rxd};
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sr <= {sr[6:0], core_rxd};
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// generate counter
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// generate counter
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always @(posedge clk or negedge aresetn)
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always @(posedge clk or negedge aresetn)
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if (!aresetn)
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if (!aresetn)
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dcnt <= #1 3'h0;
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dcnt <= 3'h0;
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else if (!sresetn)
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else if (!sresetn)
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dcnt <= #1 3'h0;
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dcnt <= 3'h0;
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else if (ld)
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else if (ld)
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dcnt <= #1 3'h7;
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dcnt <= 3'h7;
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else if (shift)
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else if (shift)
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dcnt <= #1 dcnt - 3'h1;
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dcnt <= dcnt - 3'h1;
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assign cnt_done = ~(|dcnt);
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assign cnt_done = ~(|dcnt);
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//
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//
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// state machine
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// state machine
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//
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//
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reg [4:0] c_state; // synopsys enum_state
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reg [4:0] c_state; // synopsys enum_state
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always @(posedge clk or negedge aresetn)
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always @(posedge clk or negedge aresetn)
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if (!aresetn)
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if (!aresetn)
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begin
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begin
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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core_txd <= #1 1'b0;
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core_txd <= 1'b0;
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shift <= #1 1'b0;
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shift <= 1'b0;
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ld <= #1 1'b0;
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ld <= 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= 1'b0;
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c_state <= #1 ST_IDLE;
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c_state <= ST_IDLE;
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ack_out <= #1 1'b0;
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ack_out <= 1'b0;
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end
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end
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else if (!sresetn | i2c_al)
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else if (!sresetn | i2c_al)
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begin
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begin
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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core_txd <= #1 1'b0;
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core_txd <= 1'b0;
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shift <= #1 1'b0;
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shift <= 1'b0;
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ld <= #1 1'b0;
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ld <= 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= 1'b0;
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c_state <= #1 ST_IDLE;
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c_state <= ST_IDLE;
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ack_out <= #1 1'b0;
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ack_out <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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// initially reset all signals
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// initially reset all signals
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core_txd <= #1 sr[7];
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core_txd <= sr[7];
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shift <= #1 1'b0;
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shift <= 1'b0;
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ld <= #1 1'b0;
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ld <= 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= 1'b0;
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case (c_state) // synopsys full_case parallel_case
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case (c_state) // synopsys full_case parallel_case
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ST_IDLE:
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ST_IDLE:
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if (go)
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if (go)
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begin
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begin
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if (start)
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if (start)
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begin
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begin
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c_state <= #1 ST_START;
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c_state <= ST_START;
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core_cmd <= #1 `I2C_CMD_START;
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core_cmd <= `I2C_CMD_START;
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end
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end
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else if (read)
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else if (read)
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begin
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begin
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c_state <= #1 ST_READ;
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c_state <= ST_READ;
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core_cmd <= #1 `I2C_CMD_READ;
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core_cmd <= `I2C_CMD_READ;
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end
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end
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else if (write)
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else if (write)
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begin
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begin
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c_state <= #1 ST_WRITE;
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c_state <= ST_WRITE;
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core_cmd <= #1 `I2C_CMD_WRITE;
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core_cmd <= `I2C_CMD_WRITE;
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end
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end
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else // stop
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else // stop
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begin
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begin
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c_state <= #1 ST_STOP;
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c_state <= ST_STOP;
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core_cmd <= #1 `I2C_CMD_STOP;
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core_cmd <= `I2C_CMD_STOP;
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end
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end
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ld <= #1 1'b1;
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ld <= 1'b1;
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end
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end
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ST_START:
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ST_START:
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if (core_ack)
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if (core_ack)
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begin
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begin
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if (read)
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if (read)
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begin
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begin
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c_state <= #1 ST_READ;
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c_state <= ST_READ;
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core_cmd <= #1 `I2C_CMD_READ;
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core_cmd <= `I2C_CMD_READ;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_WRITE;
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c_state <= ST_WRITE;
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core_cmd <= #1 `I2C_CMD_WRITE;
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core_cmd <= `I2C_CMD_WRITE;
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end
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end
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ld <= #1 1'b1;
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ld <= 1'b1;
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end
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end
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ST_WRITE:
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ST_WRITE:
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if (core_ack)
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if (core_ack)
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if (cnt_done)
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if (cnt_done)
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begin
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begin
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c_state <= #1 ST_ACK;
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c_state <= ST_ACK;
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core_cmd <= #1 `I2C_CMD_READ;
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core_cmd <= `I2C_CMD_READ;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_WRITE; // stay in same state
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c_state <= ST_WRITE; // stay in same state
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core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
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core_cmd <= `I2C_CMD_WRITE; // write next bit
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shift <= #1 1'b1;
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shift <= 1'b1;
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end
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end
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ST_READ:
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ST_READ:
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if (core_ack)
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if (core_ack)
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begin
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begin
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if (cnt_done)
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if (cnt_done)
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begin
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begin
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c_state <= #1 ST_ACK;
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c_state <= ST_ACK;
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core_cmd <= #1 `I2C_CMD_WRITE;
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core_cmd <= `I2C_CMD_WRITE;
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end
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end
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else
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else
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begin
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begin
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c_state <= #1 ST_READ; // stay in same state
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c_state <= ST_READ; // stay in same state
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core_cmd <= #1 `I2C_CMD_READ; // read next bit
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core_cmd <= `I2C_CMD_READ; // read next bit
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end
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end
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|
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shift <= #1 1'b1;
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shift <= 1'b1;
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core_txd <= #1 ack_in;
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core_txd <= ack_in;
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end
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end
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|
|
ST_ACK:
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ST_ACK:
|
if (core_ack)
|
if (core_ack)
|
begin
|
begin
|
if (stop)
|
if (stop)
|
begin
|
begin
|
c_state <= #1 ST_STOP;
|
c_state <= ST_STOP;
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core_cmd <= #1 `I2C_CMD_STOP;
|
core_cmd <= `I2C_CMD_STOP;
|
end
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end
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else
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else
|
begin
|
begin
|
c_state <= #1 ST_IDLE;
|
c_state <= ST_IDLE;
|
core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= `I2C_CMD_NOP;
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|
|
// generate command acknowledge signal
|
// generate command acknowledge signal
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cmd_ack <= #1 1'b1;
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cmd_ack <= 1'b1;
|
end
|
end
|
|
|
// assign ack_out output to bit_controller_rxd (contains last received bit)
|
// assign ack_out output to bit_controller_rxd (contains last received bit)
|
ack_out <= #1 core_rxd;
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ack_out <= core_rxd;
|
|
|
core_txd <= #1 1'b1;
|
core_txd <= 1'b1;
|
end
|
end
|
else
|
else
|
core_txd <= #1 ack_in;
|
core_txd <= ack_in;
|
|
|
ST_STOP:
|
ST_STOP:
|
if (core_ack)
|
if (core_ack)
|
begin
|
begin
|
c_state <= #1 ST_IDLE;
|
c_state <= ST_IDLE;
|
core_cmd <= #1 `I2C_CMD_NOP;
|
core_cmd <= `I2C_CMD_NOP;
|
|
|
// generate command acknowledge signal
|
// generate command acknowledge signal
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cmd_ack <= #1 1'b1;
|
cmd_ack <= 1'b1;
|
end
|
end
|
|
default: c_state <= ST_IDLE;
|
|
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
endmodule
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|
|
