//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS 8051 cores common library Module ////
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//// OMS 8051 cores common library Module ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Revision : Nov 26, 2016
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//// v-0.0 - Dinesh.A, Nov 26, 2016
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//// 1. Initial Version
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//// v-0.1 - Dinesh.A, Jan 19, 2017
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//// 1. Lint warning fixes, Seperated resetable and non
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// resetable logic
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/**********************************************
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/**********************************************
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Web-bone cross bar M-Master By S-Slave
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Web-bone cross bar M-Master By S-Slave
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**********************************************/
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**********************************************/
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module wb_crossbar (
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module wb_crossbar (
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rst_n ,
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rst_n ,
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clk ,
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clk ,
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// Master Interface Signal
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// Master Interface Signal
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wbd_taddr_master ,
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wbd_taddr_master ,
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wbd_din_master ,
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wbd_din_master ,
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wbd_dout_master ,
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wbd_dout_master ,
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wbd_adr_master ,
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wbd_adr_master ,
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wbd_be_master ,
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wbd_be_master ,
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wbd_we_master ,
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wbd_we_master ,
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wbd_ack_master ,
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wbd_ack_master ,
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wbd_stb_master ,
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wbd_stb_master ,
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wbd_cyc_master ,
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wbd_cyc_master ,
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wbd_err_master ,
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wbd_err_master ,
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wbd_rty_master ,
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wbd_rty_master ,
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// Slave Interface Signal
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// Slave Interface Signal
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wbd_din_slave ,
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wbd_din_slave ,
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wbd_dout_slave ,
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wbd_dout_slave ,
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wbd_adr_slave ,
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wbd_adr_slave ,
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wbd_be_slave ,
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wbd_be_slave ,
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wbd_we_slave ,
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wbd_we_slave ,
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wbd_ack_slave ,
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wbd_ack_slave ,
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wbd_stb_slave ,
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wbd_stb_slave ,
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wbd_cyc_slave ,
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wbd_cyc_slave ,
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wbd_err_slave ,
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wbd_err_slave ,
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wbd_rty_slave
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wbd_rty_slave
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);
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);
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parameter WB_SLAVE = 4 ;
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parameter WB_SLAVE = 4 ;
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parameter WB_MASTER = 4 ;
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parameter WB_MASTER = 4 ;
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parameter D_WD = 16; // Data Width
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parameter D_WD = 16; // Data Width
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parameter BE_WD = 2; // Byte Enable
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parameter BE_WD = 2; // Byte Enable
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parameter ADR_WD = 28; // Address Width
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parameter ADR_WD = 28; // Address Width
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parameter TAR_WD = 4; // Target Width
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parameter TAR_WD = 4; // Target Width
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input clk; // CLK_I The clock input [CLK_I] coordinates all activities
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input clk; // CLK_I The clock input [CLK_I] coordinates all activities
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// for the internal logic within the WISHBONE interconnect.
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// for the internal logic within the WISHBONE interconnect.
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// All WISHBONE output signals are registered at the
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// All WISHBONE output signals are registered at the
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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// All WISHBONE input signals must be stable before the
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// All WISHBONE input signals must be stable before the
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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input rst_n; // RST_I The reset input [RST_I] forces the WISHBONE interface
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input rst_n; // RST_I The reset input [RST_I] forces the WISHBONE interface
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// to restart. Furthermore, all internal self-starting state
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// to restart. Furthermore, all internal self-starting state
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// machines will be forced into an initial state.
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// machines will be forced into an initial state.
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input [(WB_MASTER *TAR_WD)-1:0] wbd_taddr_master; // target address from master
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input [(WB_MASTER *TAR_WD)-1:0] wbd_taddr_master; // target address from master
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input [WB_MASTER-1:0] wbd_stb_master;
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input [WB_MASTER-1:0] wbd_stb_master;
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// STB_O The strobe output [STB_O] indicates a valid data
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// STB_O The strobe output [STB_O] indicates a valid data
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// transfer cycle. It is used to qualify various other signals
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// transfer cycle. It is used to qualify various other signals
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// on the interface such as [SEL_O(7..0)]. The SLAVE must
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// on the interface such as [SEL_O(7..0)]. The SLAVE must
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// assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
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// assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
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// response to every assertion of the [STB_O] signal.
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// response to every assertion of the [STB_O] signal.
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output [WB_SLAVE-1:0] wbd_stb_slave;
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output [WB_SLAVE-1:0] wbd_stb_slave;
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// STB_O The strobe output [STB_O] indicates a valid data
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// STB_O The strobe output [STB_O] indicates a valid data
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// transfer cycle. It is used to qualify various other signals
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// transfer cycle. It is used to qualify various other signals
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// on the interface such as [SEL_O(7..0)]. The SLAVE must
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// on the interface such as [SEL_O(7..0)]. The SLAVE must
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// assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
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// assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
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// response to every assertion of the [STB_O] signal.
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// response to every assertion of the [STB_O] signal.
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input [WB_MASTER-1:0] wbd_we_master;
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input [WB_MASTER-1:0] wbd_we_master;
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// WE_O The write enable output [WE_O] indicates whether the
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// WE_O The write enable output [WE_O] indicates whether the
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// current local bus cycle is a READ or WRITE cycle. The
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// current local bus cycle is a READ or WRITE cycle. The
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// signal is negated during READ cycles, and is asserted
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// signal is negated during READ cycles, and is asserted
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// during WRITE cycles.
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// during WRITE cycles.
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output [WB_SLAVE-1:0] wbd_we_slave;
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output [WB_SLAVE-1:0] wbd_we_slave;
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// WE_O The write enable output [WE_O] indicates whether the
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// WE_O The write enable output [WE_O] indicates whether the
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// current local bus cycle is a READ or WRITE cycle. The
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// current local bus cycle is a READ or WRITE cycle. The
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// signal is negated during READ cycles, and is asserted
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// signal is negated during READ cycles, and is asserted
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// during WRITE cycles.
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// during WRITE cycles.
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output [WB_MASTER-1:0] wbd_ack_master;
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output [WB_MASTER-1:0] wbd_ack_master;
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// The acknowledge input [ACK_I], when asserted,
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// The acknowledge input [ACK_I], when asserted,
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// indicates the termination of a normal bus cycle.
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// indicates the termination of a normal bus cycle.
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// Also see the [ERR_I] and [RTY_I] signal descriptions.
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// Also see the [ERR_I] and [RTY_I] signal descriptions.
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input [WB_SLAVE-1:0] wbd_ack_slave;
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input [WB_SLAVE-1:0] wbd_ack_slave;
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// The acknowledge input [ACK_I], when asserted,
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// The acknowledge input [ACK_I], when asserted,
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// indicates the termination of a normal bus cycle.
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// indicates the termination of a normal bus cycle.
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// Also see the [ERR_I] and [RTY_I] signal descriptions.
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// Also see the [ERR_I] and [RTY_I] signal descriptions.
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input [(WB_MASTER *ADR_WD)-1:0] wbd_adr_master;
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input [(WB_MASTER *ADR_WD)-1:0] wbd_adr_master;
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// The address output array [ADR_O(63..0)] is used
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// The address output array [ADR_O(63..0)] is used
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// to pass a binary address, with the most significant
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// to pass a binary address, with the most significant
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// address bit at the higher numbered end of the signal array.
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// address bit at the higher numbered end of the signal array.
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// The lower array boundary is specific to the data port size.
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// The lower array boundary is specific to the data port size.
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// The higher array boundary is core-specific.
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// The higher array boundary is core-specific.
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// In some cases (such as FIFO interfaces)
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// In some cases (such as FIFO interfaces)
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// the array may not be present on the interface.
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// the array may not be present on the interface.
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output [(WB_SLAVE *ADR_WD)-1:0] wbd_adr_slave;
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output [(WB_SLAVE *ADR_WD)-1:0] wbd_adr_slave;
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// The address output array [ADR_O(63..0)] is used
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// The address output array [ADR_O(63..0)] is used
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// to pass a binary address, with the most significant
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// to pass a binary address, with the most significant
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// address bit at the higher numbered end of the signal array.
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// address bit at the higher numbered end of the signal array.
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// The lower array boundary is specific to the data port size.
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// The lower array boundary is specific to the data port size.
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// The higher array boundary is core-specific.
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// The higher array boundary is core-specific.
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// In some cases (such as FIFO interfaces)
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// In some cases (such as FIFO interfaces)
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// the array may not be present on the interface.
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// the array may not be present on the interface.
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input [(WB_MASTER * BE_WD)-1:0] wbd_be_master; // Byte Enable
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input [(WB_MASTER * BE_WD)-1:0] wbd_be_master; // Byte Enable
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// SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
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// SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
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// where valid data is expected on the [DAT_I(63..0)] signal
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// where valid data is expected on the [DAT_I(63..0)] signal
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// array during READ cycles, and where it is placed on the
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// array during READ cycles, and where it is placed on the
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// [DAT_O(63..0)] signal array during WRITE cycles.
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// [DAT_O(63..0)] signal array during WRITE cycles.
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// Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
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// Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
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// signal descriptions.
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// signal descriptions.
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output [(WB_SLAVE * BE_WD)-1:0] wbd_be_slave; // Byte Enable
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output [(WB_SLAVE * BE_WD)-1:0] wbd_be_slave; // Byte Enable
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// SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
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// SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
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// where valid data is expected on the [DAT_I(63..0)] signal
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// where valid data is expected on the [DAT_I(63..0)] signal
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// array during READ cycles, and where it is placed on the
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// array during READ cycles, and where it is placed on the
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// [DAT_O(63..0)] signal array during WRITE cycles.
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// [DAT_O(63..0)] signal array during WRITE cycles.
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// Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
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// Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
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// signal descriptions.
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// signal descriptions.
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input [WB_MASTER -1:0] wbd_cyc_master;
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input [WB_MASTER -1:0] wbd_cyc_master;
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// CYC_O The cycle output [CYC_O], when asserted,
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// CYC_O The cycle output [CYC_O], when asserted,
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// indicates that a valid bus cycle is in progress.
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// indicates that a valid bus cycle is in progress.
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// The signal is asserted for the duration of all bus cycles.
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// The signal is asserted for the duration of all bus cycles.
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// For example, during a BLOCK transfer cycle there can be
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// For example, during a BLOCK transfer cycle there can be
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// multiple data transfers. The [CYC_O] signal is asserted
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// multiple data transfers. The [CYC_O] signal is asserted
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// during the first data transfer, and remains asserted
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// during the first data transfer, and remains asserted
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// until the last data transfer. The [CYC_O] signal is useful
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// until the last data transfer. The [CYC_O] signal is useful
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// for interfaces with multi-port interfaces
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// for interfaces with multi-port interfaces
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// (such as dual port memories). In these cases,
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// (such as dual port memories). In these cases,
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// the [CYC_O] signal requests use of a common bus from an
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// the [CYC_O] signal requests use of a common bus from an
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// arbiter. Once the arbiter grants the bus to the MASTER,
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// arbiter. Once the arbiter grants the bus to the MASTER,
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// it is held until [CYC_O] is negated.
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// it is held until [CYC_O] is negated.
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output [WB_SLAVE -1:0] wbd_cyc_slave;
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output [WB_SLAVE -1:0] wbd_cyc_slave;
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// CYC_O The cycle output [CYC_O], when asserted,
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// CYC_O The cycle output [CYC_O], when asserted,
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// indicates that a valid bus cycle is in progress.
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// indicates that a valid bus cycle is in progress.
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// The signal is asserted for the duration of all bus cycles.
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// The signal is asserted for the duration of all bus cycles.
|
// For example, during a BLOCK transfer cycle there can be
|
// For example, during a BLOCK transfer cycle there can be
|
// multiple data transfers. The [CYC_O] signal is asserted
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// multiple data transfers. The [CYC_O] signal is asserted
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// during the first data transfer, and remains asserted
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// during the first data transfer, and remains asserted
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// until the last data transfer. The [CYC_O] signal is useful
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// until the last data transfer. The [CYC_O] signal is useful
|
// for interfaces with multi-port interfaces
|
// for interfaces with multi-port interfaces
|
// (such as dual port memories). In these cases,
|
// (such as dual port memories). In these cases,
|
// the [CYC_O] signal requests use of a common bus from an
|
// the [CYC_O] signal requests use of a common bus from an
|
// arbiter. Once the arbiter grants the bus to the MASTER,
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// arbiter. Once the arbiter grants the bus to the MASTER,
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// it is held until [CYC_O] is negated.
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// it is held until [CYC_O] is negated.
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|
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input [(WB_MASTER * D_WD)-1:0] wbd_din_master;
|
input [(WB_MASTER * D_WD)-1:0] wbd_din_master;
|
// DAT_I(63..0) The data input array [DAT_I(63..0)] is
|
// DAT_I(63..0) The data input array [DAT_I(63..0)] is
|
// used to pass binary data. The array boundaries are
|
// used to pass binary data. The array boundaries are
|
// determined by the port size. Also see the [DAT_O(63..0)]
|
// determined by the port size. Also see the [DAT_O(63..0)]
|
// and [SEL_O(7..0)] signal descriptions.
|
// and [SEL_O(7..0)] signal descriptions.
|
|
|
output [(WB_SLAVE * D_WD)-1:0] wbd_din_slave;
|
output [(WB_SLAVE * D_WD)-1:0] wbd_din_slave;
|
// DAT_I(63..0) The data input array [DAT_I(63..0)] is
|
// DAT_I(63..0) The data input array [DAT_I(63..0)] is
|
// used to pass binary data. The array boundaries are
|
// used to pass binary data. The array boundaries are
|
// determined by the port size. Also see the [DAT_O(63..0)]
|
// determined by the port size. Also see the [DAT_O(63..0)]
|
// and [SEL_O(7..0)] signal descriptions.
|
// and [SEL_O(7..0)] signal descriptions.
|
|
|
output [(WB_MASTER * D_WD)-1:0] wbd_dout_master;
|
output [(WB_MASTER * D_WD)-1:0] wbd_dout_master;
|
// DAT_O(63..0) The data output array [DAT_O(63..0)] is
|
// DAT_O(63..0) The data output array [DAT_O(63..0)] is
|
// used to pass binary data. The array boundaries are
|
// used to pass binary data. The array boundaries are
|
// determined by the port size. Also see the [DAT_I(63..0)]
|
// determined by the port size. Also see the [DAT_I(63..0)]
|
// and [SEL_O(7..0)] signal descriptions.
|
// and [SEL_O(7..0)] signal descriptions.
|
input [(WB_SLAVE * D_WD)-1:0] wbd_dout_slave;
|
input [(WB_SLAVE * D_WD)-1:0] wbd_dout_slave;
|
// DAT_O(63..0) The data output array [DAT_O(63..0)] is
|
// DAT_O(63..0) The data output array [DAT_O(63..0)] is
|
// used to pass binary data. The array boundaries are
|
// used to pass binary data. The array boundaries are
|
// determined by the port size. Also see the [DAT_I(63..0)]
|
// determined by the port size. Also see the [DAT_I(63..0)]
|
// and [SEL_O(7..0)] signal descriptions.
|
// and [SEL_O(7..0)] signal descriptions.
|
|
|
output [WB_MASTER -1:0] wbd_err_master;
|
output [WB_MASTER -1:0] wbd_err_master;
|
// ERR_I The error input [ERR_I] indicates an abnormal
|
// ERR_I The error input [ERR_I] indicates an abnormal
|
// cycle termination. The source of the error, and the
|
// cycle termination. The source of the error, and the
|
// response generated by the MASTER is defined by the IP core
|
// response generated by the MASTER is defined by the IP core
|
// supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
|
// supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
|
// and [RTY_I] signal descriptions.
|
// and [RTY_I] signal descriptions.
|
input [WB_SLAVE -1:0] wbd_err_slave;
|
input [WB_SLAVE -1:0] wbd_err_slave;
|
// ERR_I The error input [ERR_I] indicates an abnormal
|
// ERR_I The error input [ERR_I] indicates an abnormal
|
// cycle termination. The source of the error, and the
|
// cycle termination. The source of the error, and the
|
// response generated by the MASTER is defined by the IP core
|
// response generated by the MASTER is defined by the IP core
|
// supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
|
// supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
|
// and [RTY_I] signal descriptions.
|
// and [RTY_I] signal descriptions.
|
|
|
output [WB_MASTER -1:0] wbd_rty_master;
|
output [WB_MASTER -1:0] wbd_rty_master;
|
// RTY_I The retry input [RTY_I] indicates that the indicates
|
// RTY_I The retry input [RTY_I] indicates that the indicates
|
// that the interface is not ready to accept or send data, and
|
// that the interface is not ready to accept or send data, and
|
// that the cycle should be retried. When and how the cycle is
|
// that the cycle should be retried. When and how the cycle is
|
// retried is defined by the IP core supplier in the WISHBONE
|
// retried is defined by the IP core supplier in the WISHBONE
|
// DATASHEET. Also see the [ERR_I] and [RTY_I] signal
|
// DATASHEET. Also see the [ERR_I] and [RTY_I] signal
|
// descriptions.
|
// descriptions.
|
input [WB_SLAVE -1:0] wbd_rty_slave;
|
input [WB_SLAVE -1:0] wbd_rty_slave;
|
// RTY_I The retry input [RTY_I] indicates that the indicates
|
// RTY_I The retry input [RTY_I] indicates that the indicates
|
// that the interface is not ready to accept or send data, and
|
// that the interface is not ready to accept or send data, and
|
// that the cycle should be retried. When and how the cycle is
|
// that the cycle should be retried. When and how the cycle is
|
// retried is defined by the IP core supplier in the WISHBONE
|
// retried is defined by the IP core supplier in the WISHBONE
|
// DATASHEET. Also see the [ERR_I] and [RTY_I] signal
|
// DATASHEET. Also see the [ERR_I] and [RTY_I] signal
|
// descriptions.
|
// descriptions.
|
|
|
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reg [WB_MASTER-1:0] wbd_ack_master;
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reg [WB_MASTER-1:0] wbd_ack_master;
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reg [WB_MASTER-1:0] wbd_err_master;
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reg [WB_MASTER-1:0] wbd_err_master;
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reg [WB_MASTER-1:0] wbd_rty_master;
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reg [WB_MASTER-1:0] wbd_rty_master;
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reg [WB_MASTER-1:0] master_busy; // master busy flag
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reg [WB_MASTER-1:0] master_busy; // master busy flag
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reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
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reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
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reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
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reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
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reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
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reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
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reg [TAR_WD-1 :0] cur_target_id;
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wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
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wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
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wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
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wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
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reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
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reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
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wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
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wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
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wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
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wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
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|
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reg [WB_SLAVE-1:0] wbd_stb_slave;
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reg [WB_SLAVE-1:0] wbd_stb_slave;
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reg [WB_SLAVE-1:0] wbd_we_slave;
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reg [WB_SLAVE-1:0] wbd_we_slave;
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reg [WB_SLAVE-1:0] wbd_cyc_slave;
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reg [WB_SLAVE-1:0] wbd_cyc_slave;
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wire [D_WD-1:0] wbd_dout_slave_t[WB_SLAVE-1:0]; // target data towards master
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wire [D_WD-1:0] wbd_dout_slave_t[WB_SLAVE-1:0]; // target data towards master
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|
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reg [D_WD-1:0] wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [D_WD-1:0] wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master
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|
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integer i,k,l;
|
integer i,k,l,n;
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|
|
|
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/**********************************************************
|
/**********************************************************
|
Re-Arraging the array in seperate two dimensional information
|
Re-Arraging the array in seperate two dimensional information
|
***********************************************************/
|
***********************************************************/
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|
|
genvar j,m;
|
genvar j,m;
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generate
|
generate
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|
|
// Connect the Master Mux
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// Connect the Master Mux
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for(j=0; j < WB_MASTER ; j = j + 1) begin : master_expand
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for(j=0; j < WB_MASTER ; j = j + 1) begin : master_expand
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assign wbd_taddr_master_t[j] = wbd_taddr_master[((j+1)*TAR_WD)-1:j * TAR_WD];
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assign wbd_taddr_master_t[j] = wbd_taddr_master[((j+1)*TAR_WD)-1:j * TAR_WD];
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assign wbd_din_master_t[j] = wbd_din_master[((j+1)*D_WD)-1:j * D_WD];
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assign wbd_din_master_t[j] = wbd_din_master[((j+1)*D_WD)-1:j * D_WD];
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assign wbd_adr_master_t[j] = wbd_adr_master[((j+1)*ADR_WD)-1:j * ADR_WD];
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assign wbd_adr_master_t[j] = wbd_adr_master[((j+1)*ADR_WD)-1:j * ADR_WD];
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assign wbd_be_master_t[j] = wbd_be_master[((j+1)*BE_WD)-1:j * BE_WD];
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assign wbd_be_master_t[j] = wbd_be_master[((j+1)*BE_WD)-1:j * BE_WD];
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|
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assign wbd_dout_master[((j+1)*D_WD)-1:j * D_WD] = wbd_dout_master_t[j];
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assign wbd_dout_master[((j+1)*D_WD)-1:j * D_WD] = wbd_dout_master_t[j];
|
end
|
end
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|
|
// Connect the Slave Mux
|
// Connect the Slave Mux
|
for(m=0; m < WB_SLAVE ; m = m + 1) begin : slave_expand
|
for(m=0; m < WB_SLAVE ; m = m + 1) begin : slave_expand
|
assign wbd_din_slave[((m+1)*D_WD)-1:m * D_WD] = wbd_din_slave_t[m];
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assign wbd_din_slave[((m+1)*D_WD)-1:m * D_WD] = wbd_din_slave_t[m];
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assign wbd_adr_slave[((m+1)*ADR_WD)-1:m * ADR_WD] = wbd_adr_slave_t[m];
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assign wbd_adr_slave[((m+1)*ADR_WD)-1:m * ADR_WD] = wbd_adr_slave_t[m];
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assign wbd_be_slave[((m+1)*BE_WD)-1:m * BE_WD] = wbd_be_slave_t[m];
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assign wbd_be_slave[((m+1)*BE_WD)-1:m * BE_WD] = wbd_be_slave_t[m];
|
|
|
assign wbd_dout_slave_t[m] = wbd_dout_slave[((m+1)*D_WD)-1:m * D_WD];
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assign wbd_dout_slave_t[m] = wbd_dout_slave[((m+1)*D_WD)-1:m * D_WD];
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @* begin
|
always @* begin
|
for(k = 0; k < WB_MASTER; k = k + 1) begin
|
for(k = 0; k < WB_MASTER; k = k + 1) begin
|
if(master_busy[k] == 1) begin
|
if(master_busy[k] == 1) begin
|
wbd_dout_master_t[k] = wbd_dout_slave_t[master_mx_id[k]];
|
wbd_dout_master_t[k] = wbd_dout_slave_t[master_mx_id[k]];
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wbd_ack_master[k] = wbd_ack_slave[master_mx_id[k]];
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wbd_ack_master[k] = wbd_ack_slave[master_mx_id[k]];
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wbd_err_master[k] = wbd_err_slave[master_mx_id[k]];
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wbd_err_master[k] = wbd_err_slave[master_mx_id[k]];
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wbd_rty_master[k] = wbd_rty_slave[master_mx_id[k]];
|
wbd_rty_master[k] = wbd_rty_slave[master_mx_id[k]];
|
end else begin
|
end else begin
|
wbd_dout_master_t[k] = 0;
|
wbd_dout_master_t[k] = 0;
|
wbd_ack_master[k] = 0;
|
wbd_ack_master[k] = 0;
|
wbd_err_master[k] = 0;
|
wbd_err_master[k] = 0;
|
wbd_rty_master[k] = 0;
|
wbd_rty_master[k] = 0;
|
end
|
end
|
end
|
end
|
for(l = 0; l < WB_SLAVE; l = l + 1) begin
|
for(l = 0; l < WB_SLAVE; l = l + 1) begin
|
if(slave_busy[l] == 1) begin
|
if(slave_busy[l] == 1) begin
|
wbd_din_slave_t[l] = wbd_din_master_t[slave_mx_id[l]];
|
wbd_din_slave_t[l] = wbd_din_master_t[slave_mx_id[l]];
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wbd_adr_slave_t[l] = wbd_adr_master_t[slave_mx_id[l]];
|
wbd_adr_slave_t[l] = wbd_adr_master_t[slave_mx_id[l]];
|
wbd_be_slave_t[l] = wbd_be_master_t[slave_mx_id[l]];
|
wbd_be_slave_t[l] = wbd_be_master_t[slave_mx_id[l]];
|
wbd_stb_slave[l] = wbd_stb_master[slave_mx_id[l]];
|
wbd_stb_slave[l] = wbd_stb_master[slave_mx_id[l]];
|
wbd_we_slave[l] = wbd_we_master[slave_mx_id[l]];
|
wbd_we_slave[l] = wbd_we_master[slave_mx_id[l]];
|
wbd_cyc_slave[l] = wbd_cyc_master[slave_mx_id[l]];
|
wbd_cyc_slave[l] = wbd_cyc_master[slave_mx_id[l]];
|
end else begin
|
end else begin
|
wbd_din_slave_t[l] = 0;
|
wbd_din_slave_t[l] = 0;
|
wbd_adr_slave_t[l] = 0;
|
wbd_adr_slave_t[l] = 0;
|
wbd_be_slave_t[l] = 0;
|
wbd_be_slave_t[l] = 0;
|
wbd_stb_slave[l] = 0;
|
wbd_stb_slave[l] = 0;
|
wbd_we_slave[l] = 0;
|
wbd_we_slave[l] = 0;
|
wbd_cyc_slave[l] = 0;
|
wbd_cyc_slave[l] = 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
/*******************************************************
|
/*******************************************************
|
Parsing through the master and deciding on mux connectio
|
Parsing through the master and deciding on mux connectio
|
Step-1: analysis the master from 0 to total master
|
Step-1: analysis the master from 0 to total master
|
Step-2: If the previously master is not busy,
|
Step-2: If the previously master is not busy,
|
Then check for any new request from the master and
|
Then check for any new request from the master and
|
check corresponding slave is free or not. If there is
|
check corresponding slave is free or not. If there is
|
master request and requesting slave is free.
|
master request and requesting slave is free.
|
Then set the master max id to slave id &
|
Then set the master max id to slave id &
|
requesting slave to master number & set the master
|
requesting slave to master number & set the master
|
and slave busy flag
|
and slave busy flag
|
Step-3: If the previous state of master is busy and bus-cycle
|
Step-3: If the previous state of master is busy and bus-cycle
|
is de-asserted, then reset the master and corresponding
|
is de-asserted, then reset the master and corresponding
|
slave busy flag
|
slave busy flag
|
|
|
*********************************************************/
|
*********************************************************/
|
|
|
always @(negedge rst_n or posedge clk) begin
|
always @(negedge rst_n or posedge clk) begin
|
if(rst_n == 0) begin
|
if(rst_n == 0) begin
|
master_busy <= 0;
|
master_busy <= 0;
|
slave_busy <= 0;
|
slave_busy <= 0;
|
end else begin
|
end else begin
|
for(i = 0; i < WB_MASTER; i = i + 1) begin
|
for(i = 0; i < WB_MASTER; i = i + 1) begin
|
cur_target_id = wbd_taddr_master_t[i];
|
|
if(master_busy[i] == 0) begin
|
if(master_busy[i] == 0) begin
|
if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
|
if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
|
master_mx_id[i] <= wbd_taddr_master_t[i];
|
|
slave_mx_id [wbd_taddr_master_t[i]] <= i;
|
|
slave_busy[wbd_taddr_master_t[i]] <= 1;
|
slave_busy[wbd_taddr_master_t[i]] <= 1;
|
master_busy[i] <= 1;
|
master_busy[i] <= 1;
|
// synopsys translate_off
|
|
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
|
|
// synopsys translate_on
|
|
end
|
end
|
end else if(wbd_cyc_master[i] == 0) begin
|
end else if(wbd_cyc_master[i] == 0) begin
|
if(master_busy[i] == 1) begin
|
|
// synopsys translate_off
|
|
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
|
|
// synopsys translate_on
|
|
end
|
|
master_busy[i] <= 0;
|
master_busy[i] <= 0;
|
slave_busy[wbd_taddr_master_t[i]] <= 0;
|
slave_busy[wbd_taddr_master_t[i]] <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
// Seperated non resetable two dimensional reg
|
|
always @(posedge clk) begin
|
|
for(n = 0; n < WB_MASTER; n = n + 1) begin
|
|
if(master_busy[n] == 0) begin
|
|
if(wbd_stb_master[n] & slave_busy[wbd_taddr_master_t[n]] == 0) begin
|
|
master_mx_id[n] <= wbd_taddr_master_t[n];
|
|
slave_mx_id [wbd_taddr_master_t[n]] <= n;
|
|
// synopsys translate_off
|
|
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
|
|
// synopsys translate_on
|
|
end
|
|
end else if(wbd_cyc_master[n] == 0) begin
|
|
if(master_busy[n] == 1) begin
|
|
// synopsys translate_off
|
|
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
|
|
// synopsys translate_on
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
