//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS 8051 cores common library Module ////
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//// OMS 8051 cores common library Module ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//// Revision : Nov 26, 2016 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/**********************************************
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/**********************************************
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Web-bone , Read from Wishbone Memory and Write to internal Memory
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Web-bone , Read from Wishbone Memory and Write to internal Memory
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This block handles following task
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This block handles following task
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1. Check the Descriptor Q for not empty
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1. Check the Descriptor Q for not empty
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2. If the Descriptor Q is not empty, the read the 32 bit descriptor
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2. If the Descriptor Q is not empty, the read the 32 bit descriptor
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3. The 32 bit descriptor holds following information
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3. The 32 bit descriptor holds following information
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[11:0] - Packet Length
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[11:0] - Packet Length
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[25:12] - MSB [15:2] of Packet Start Location
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[25:12] - MSB [15:2] of Packet Start Location
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[31:26] - Packet Status
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[31:26] - Packet Status
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4. Based on the Packet Length, Read the data from external Data memory
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4. Based on the Packet Length, Read the data from external Data memory
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and write it to Internal Memory
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and write it to Internal Memory
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|
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**********************************************/
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**********************************************/
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module wb_rd_mem2mem (
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module wb_rd_mem2mem (
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rst_n ,
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rst_n ,
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clk ,
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clk ,
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// descriptor handshake
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// descriptor handshake
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cfg_desc_baddr ,
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cfg_desc_baddr ,
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desc_q_empty ,
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desc_q_empty ,
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// Master Interface Signal
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// Master Interface Signal
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mem_taddr ,
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mem_taddr ,
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mem_full ,
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mem_full ,
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mem_afull ,
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mem_afull ,
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mem_wr ,
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mem_wr ,
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mem_din ,
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mem_din ,
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// Slave Interface Signal
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// Slave Interface Signal
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wbo_dout ,
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wbo_dout ,
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wbo_taddr ,
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wbo_taddr ,
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wbo_addr ,
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wbo_addr ,
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wbo_be ,
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wbo_be ,
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wbo_we ,
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wbo_we ,
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wbo_ack ,
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wbo_ack ,
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wbo_stb ,
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wbo_stb ,
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wbo_cyc ,
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wbo_cyc ,
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wbo_err ,
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wbo_err ,
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wbo_rty
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wbo_rty
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);
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);
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parameter D_WD = 16; // Data Width
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parameter D_WD = 16; // Data Width
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parameter BE_WD = 2; // Byte Enable
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parameter BE_WD = 2; // Byte Enable
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parameter ADR_WD = 28; // Address Width
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parameter ADR_WD = 28; // Address Width
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parameter TAR_WD = 4; // Target Width
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parameter TAR_WD = 4; // Target Width
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//---------------------
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//---------------------
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// State Machine Parameter
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// State Machine Parameter
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//--------------------
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//--------------------
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|
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parameter IDLE = 0;
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parameter IDLE = 0;
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parameter DESC_RD = 1;
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parameter DESC_RD = 1;
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parameter DATA_WAIT = 2;
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parameter DATA_WAIT = 2;
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parameter TXFR = 3;
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parameter TXFR = 3;
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parameter MEM_WRITE2 = 4;
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parameter MEM_WRITE2 = 4;
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parameter MEM_WRITE3 = 5;
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parameter MEM_WRITE3 = 5;
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parameter MEM_WRITE4 = 6;
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parameter MEM_WRITE4 = 6;
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//-------------------------------------------
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//-------------------------------------------
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// Input Declaration
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// Input Declaration
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//------------------------------------------
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//------------------------------------------
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input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
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input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
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// for the internal logic within the WISHBONE interconnect.
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// for the internal logic within the WISHBONE interconnect.
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// All WISHBONE output signals are registered at the
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// All WISHBONE output signals are registered at the
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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// All WISHBONE input signals must be stable before the
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// All WISHBONE input signals must be stable before the
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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input rst_n ; // RST_I The reset input [RST_I] forces the WISHBONE interface
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input rst_n ; // RST_I The reset input [RST_I] forces the WISHBONE interface
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// to restart. Furthermore, all internal self-starting state
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// to restart. Furthermore, all internal self-starting state
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// machines will be forced into an initial state.
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// machines will be forced into an initial state.
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//---------------------------------
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//---------------------------------
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// Descriptor Interface
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// Descriptor Interface
|
//---------------------------------
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//---------------------------------
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input [15:6] cfg_desc_baddr ; // descriptor Base Address
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input [15:6] cfg_desc_baddr ; // descriptor Base Address
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input desc_q_empty ;
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input desc_q_empty ;
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//------------------------------------------
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//------------------------------------------
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// Stanard Memory Interface
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// Stanard Memory Interface
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//------------------------------------------
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//------------------------------------------
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input [TAR_WD-1:0] mem_taddr ; // target address
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input [TAR_WD-1:0] mem_taddr ; // target address
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input mem_full ; // memory full
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input mem_full ; // memory full
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input mem_afull ; // memory afull
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input mem_afull ; // memory afull
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output mem_wr ; // memory Write
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output mem_wr ; // memory Write
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output [8:0] mem_din ; // memory read data
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output [8:0] mem_din ; // memory read data
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|
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//------------------------------------------
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//------------------------------------------
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// External Memory WB Interface
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// External Memory WB Interface
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//------------------------------------------
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//------------------------------------------
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output wbo_stb ; // STB_O The strobe output [STB_O] indicates a valid data
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output wbo_stb ; // STB_O The strobe output [STB_O] indicates a valid data
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// transfer cycle. It is used to qualify various other signals
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// transfer cycle. It is used to qualify various other signals
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// on the interface such as [SEL_O(7..0)]. The SLAVE must
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// on the interface such as [SEL_O(7..0)]. The SLAVE must
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// assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
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// assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
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// response to every assertion of the [STB_O] signal.
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// response to every assertion of the [STB_O] signal.
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output wbo_we ; // WE_O The write enable output [WE_O] indicates whether the
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output wbo_we ; // WE_O The write enable output [WE_O] indicates whether the
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// current local bus cycle is a READ or WRITE cycle. The
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// current local bus cycle is a READ or WRITE cycle. The
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// signal is negated during READ cycles, and is asserted
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// signal is negated during READ cycles, and is asserted
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// during WRITE cycles.
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// during WRITE cycles.
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input wbo_ack ; // The acknowledge input [ACK_I], when asserted,
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input wbo_ack ; // The acknowledge input [ACK_I], when asserted,
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// indicates the termination of a normal bus cycle.
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// indicates the termination of a normal bus cycle.
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// Also see the [ERR_I] and [RTY_I] signal descriptions.
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// Also see the [ERR_I] and [RTY_I] signal descriptions.
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|
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output [TAR_WD-1:0] wbo_taddr;
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output [TAR_WD-1:0] wbo_taddr;
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output [ADR_WD-1:0] wbo_addr ; // The address output array [ADR_O(63..0)] is used
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output [ADR_WD-1:0] wbo_addr ; // The address output array [ADR_O(63..0)] is used
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// to pass a binary address, with the most significant
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// to pass a binary address, with the most significant
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// address bit at the higher numbered end of the signal array.
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// address bit at the higher numbered end of the signal array.
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// The lower array boundary is specific to the data port size.
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// The lower array boundary is specific to the data port size.
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// The higher array boundary is core-specific.
|
// The higher array boundary is core-specific.
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// In some cases (such as FIFO interfaces)
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// In some cases (such as FIFO interfaces)
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// the array may not be present on the interface.
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// the array may not be present on the interface.
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|
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output [BE_WD-1:0] wbo_be ; // Byte Enable
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output [BE_WD-1:0] wbo_be ; // Byte Enable
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// SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
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// SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
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// where valid data is expected on the [DAT_I(63..0)] signal
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// where valid data is expected on the [DAT_I(63..0)] signal
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// array during READ cycles, and where it is placed on the
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// array during READ cycles, and where it is placed on the
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// [DAT_O(63..0)] signal array during WRITE cycles.
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// [DAT_O(63..0)] signal array during WRITE cycles.
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// Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
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// Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
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// signal descriptions.
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// signal descriptions.
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output wbo_cyc ; // CYC_O The cycle output [CYC_O], when asserted,
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output wbo_cyc ; // CYC_O The cycle output [CYC_O], when asserted,
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// indicates that a valid bus cycle is in progress.
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// indicates that a valid bus cycle is in progress.
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// The signal is asserted for the duration of all bus cycles.
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// The signal is asserted for the duration of all bus cycles.
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// For example, during a BLOCK transfer cycle there can be
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// For example, during a BLOCK transfer cycle there can be
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// multiple data transfers. The [CYC_O] signal is asserted
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// multiple data transfers. The [CYC_O] signal is asserted
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// during the first data transfer, and remains asserted
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// during the first data transfer, and remains asserted
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// until the last data transfer. The [CYC_O] signal is useful
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// until the last data transfer. The [CYC_O] signal is useful
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// for interfaces with multi-port interfaces
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// for interfaces with multi-port interfaces
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// (such as dual port memories). In these cases,
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// (such as dual port memories). In these cases,
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// the [CYC_O] signal requests use of a common bus from an
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// the [CYC_O] signal requests use of a common bus from an
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// arbiter. Once the arbiter grants the bus to the MASTER,
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// arbiter. Once the arbiter grants the bus to the MASTER,
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// it is held until [CYC_O] is negated.
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// it is held until [CYC_O] is negated.
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input [D_WD-1:0] wbo_dout; // DAT_I(63..0) The data input array [DAT_I(63..0)] is
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input [D_WD-1:0] wbo_dout; // DAT_I(63..0) The data input array [DAT_I(63..0)] is
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// used to pass binary data. The array boundaries are
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// used to pass binary data. The array boundaries are
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// determined by the port size. Also see the [DAT_O(63..0)]
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// determined by the port size. Also see the [DAT_O(63..0)]
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// and [SEL_O(7..0)] signal descriptions.
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// and [SEL_O(7..0)] signal descriptions.
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input wbo_err; // ERR_I The error input [ERR_I] indicates an abnormal
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input wbo_err; // ERR_I The error input [ERR_I] indicates an abnormal
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// cycle termination. The source of the error, and the
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// cycle termination. The source of the error, and the
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// response generated by the MASTER is defined by the IP core
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// response generated by the MASTER is defined by the IP core
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// supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
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// supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
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// and [RTY_I] signal descriptions.
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// and [RTY_I] signal descriptions.
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input wbo_rty; // RTY_I The retry input [RTY_I] indicates that the indicates
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input wbo_rty; // RTY_I The retry input [RTY_I] indicates that the indicates
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// that the interface is not ready to accept or send data, and
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// that the interface is not ready to accept or send data, and
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// that the cycle should be retried. When and how the cycle is
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// that the cycle should be retried. When and how the cycle is
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// retried is defined by the IP core supplier in the WISHBONE
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// retried is defined by the IP core supplier in the WISHBONE
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// DATASHEET. Also see the [ERR_I] and [RTY_I] signal
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// DATASHEET. Also see the [ERR_I] and [RTY_I] signal
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// descriptions.
|
// descriptions.
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//----------------------------------------
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//----------------------------------------
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// Register Declration
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// Register Declration
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//----------------------------------------
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//----------------------------------------
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|
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reg [2:0] state ;
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reg [2:0] state ;
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reg [15:0] cnt ;
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reg [15:0] cnt ;
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reg [TAR_WD-1:0] wbo_taddr ;
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reg [TAR_WD-1:0] wbo_taddr ;
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reg [ADR_WD-1:0] wbo_addr ;
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reg [ADR_WD-1:0] wbo_addr ;
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reg wbo_stb ;
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reg wbo_stb ;
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reg wbo_we ;
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reg wbo_we ;
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reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg [15:0] mem_addr ;
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reg [15:0] mem_addr ;
|
|
|
|
|
|
|
|
|
reg [3:0] desc_ptr;
|
reg [3:0] desc_ptr;
|
reg [23:0] tWrData; // Temp Write Data
|
reg [23:0] tWrData; // Temp Write Data
|
reg [8:0] mem_din;
|
reg [8:0] mem_din;
|
reg mem_wr;
|
reg mem_wr;
|
|
|
always @(negedge rst_n or posedge clk) begin
|
always @(negedge rst_n or posedge clk) begin
|
if(rst_n == 0) begin
|
if(rst_n == 0) begin
|
state <= IDLE;
|
state <= IDLE;
|
wbo_taddr <= 0;
|
wbo_taddr <= 0;
|
wbo_addr <= 0;
|
wbo_addr <= 0;
|
wbo_stb <= 0;
|
wbo_stb <= 0;
|
wbo_we <= 0;
|
wbo_we <= 0;
|
wbo_be <= 0;
|
wbo_be <= 0;
|
wbo_cyc <= 0;
|
wbo_cyc <= 0;
|
desc_ptr <= 0;
|
desc_ptr <= 0;
|
mem_addr <= 0;
|
mem_addr <= 0;
|
mem_din <= 0;
|
mem_din <= 0;
|
tWrData <= 0;
|
tWrData <= 0;
|
mem_wr <= 0;
|
mem_wr <= 0;
|
|
cnt <= 0;
|
end
|
end
|
else begin
|
else begin
|
case(state)
|
case(state)
|
IDLE: begin
|
IDLE: begin
|
mem_wr <= 0;
|
mem_wr <= 0;
|
// Check for Descriptor Q not empty
|
// Check for Descriptor Q not empty
|
if(!desc_q_empty) begin
|
if(!desc_q_empty) begin
|
wbo_taddr <= mem_taddr;
|
wbo_taddr <= mem_taddr;
|
wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
|
wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
|
wbo_be <= 4'hF;
|
wbo_be <= 4'hF;
|
wbo_we <= 1'b0;
|
wbo_we <= 1'b0;
|
wbo_stb <= 1'b1;
|
wbo_stb <= 1'b1;
|
wbo_cyc <= 1;
|
wbo_cyc <= 1;
|
state <= DESC_RD;
|
state <= DESC_RD;
|
desc_ptr <= desc_ptr+1;
|
desc_ptr <= desc_ptr+1;
|
end
|
end
|
end
|
end
|
DESC_RD: begin
|
DESC_RD: begin
|
// wait for web-bone ack
|
// wait for web-bone ack
|
if(wbo_ack) begin
|
if(wbo_ack) begin
|
wbo_cyc <= 1'b0;
|
wbo_cyc <= 1'b0;
|
wbo_stb <= 1'b0;
|
wbo_stb <= 1'b0;
|
state <= IDLE;
|
state <= IDLE;
|
cnt <= wbo_dout[11:0];
|
cnt <= wbo_dout[11:0];
|
mem_addr <= {wbo_dout[27:12],2'b0};
|
mem_addr <= {wbo_dout[27:12],2'b0};
|
state <= DATA_WAIT;
|
state <= DATA_WAIT;
|
end
|
end
|
end
|
end
|
|
|
DATA_WAIT: begin
|
DATA_WAIT: begin
|
mem_wr <= 0; // Reset the write for handling interburst
|
mem_wr <= 0; // Reset the write for handling interburst
|
// check for internal memory not full and initiate
|
// check for internal memory not full and initiate
|
// the transfer
|
// the transfer
|
if(!(mem_full || mem_afull)) begin
|
if(!(mem_full || mem_afull)) begin
|
wbo_taddr <= mem_taddr;
|
wbo_taddr <= mem_taddr;
|
wbo_addr <= mem_addr[14:2];
|
wbo_addr <= mem_addr[14:2];
|
wbo_stb <= 1'b1;
|
wbo_stb <= 1'b1;
|
wbo_we <= 1'b0;
|
wbo_we <= 1'b0;
|
wbo_be <= 4'hF;
|
wbo_be <= 4'hF;
|
wbo_cyc <= 1'b1;
|
wbo_cyc <= 1'b1;
|
state <= TXFR;
|
state <= TXFR;
|
end
|
end
|
end
|
end
|
TXFR: begin
|
TXFR: begin
|
if(wbo_ack) begin
|
if(wbo_ack) begin
|
wbo_cyc <= 1'b0;
|
wbo_cyc <= 1'b0;
|
wbo_stb <= 1'b0;
|
wbo_stb <= 1'b0;
|
mem_addr <= mem_addr+4;
|
mem_addr <= mem_addr+4;
|
mem_din[7:0] <= wbo_dout[7:0]; // Write First Byte
|
mem_din[7:0] <= wbo_dout[7:0]; // Write First Byte
|
tWrData <= wbo_dout[31:8];
|
tWrData <= wbo_dout[31:8];
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_wr <= 1;
|
mem_wr <= 1;
|
cnt <= cnt-1;
|
cnt <= cnt-1;
|
if(cnt == 1) begin
|
if(cnt == 1) begin
|
state <= IDLE;
|
state <= IDLE;
|
end else begin
|
end else begin
|
state <= MEM_WRITE2;
|
state <= MEM_WRITE2;
|
end
|
end
|
end
|
end
|
end
|
end
|
MEM_WRITE2: begin // Write 2nd Byte
|
MEM_WRITE2: begin // Write 2nd Byte
|
if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
|
if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
|
mem_din[7:0] <= tWrData[7:0];
|
mem_din[7:0] <= tWrData[7:0];
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_wr <= 1;
|
mem_wr <= 1;
|
cnt <= cnt-1;
|
cnt <= cnt-1;
|
if(cnt == 1) begin
|
if(cnt == 1) begin
|
state <= IDLE;
|
state <= IDLE;
|
end else begin
|
end else begin
|
state <= MEM_WRITE3;
|
state <= MEM_WRITE3;
|
end
|
end
|
end else begin
|
end else begin
|
mem_wr <= 0;
|
mem_wr <= 0;
|
end
|
end
|
end
|
end
|
MEM_WRITE3: begin // Write 3rd Byte
|
MEM_WRITE3: begin // Write 3rd Byte
|
if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
|
if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
|
mem_din[7:0] <= tWrData[15:8];
|
mem_din[7:0] <= tWrData[15:8];
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_wr <= 1;
|
mem_wr <= 1;
|
cnt <= cnt-1;
|
cnt <= cnt-1;
|
if(cnt == 1) begin
|
if(cnt == 1) begin
|
state <= IDLE;
|
state <= IDLE;
|
end else begin
|
end else begin
|
state <= MEM_WRITE4;
|
state <= MEM_WRITE4;
|
end
|
end
|
end else begin
|
end else begin
|
mem_wr <= 0;
|
mem_wr <= 0;
|
end
|
end
|
end
|
end
|
MEM_WRITE4: begin // Write 4th Byte
|
MEM_WRITE4: begin // Write 4th Byte
|
if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
|
if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
|
mem_din[7:0] <= tWrData[23:16];
|
mem_din[7:0] <= tWrData[23:16];
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
|
mem_wr <= 1;
|
mem_wr <= 1;
|
cnt <= cnt-1;
|
cnt <= cnt-1;
|
if(cnt == 1) begin
|
if(cnt == 1) begin
|
state <= IDLE;
|
state <= IDLE;
|
end else begin
|
end else begin
|
state <= DATA_WAIT;
|
state <= DATA_WAIT;
|
end
|
end
|
end else begin
|
end else begin
|
mem_wr <= 0;
|
mem_wr <= 0;
|
end
|
end
|
end
|
end
|
|
default: state <= IDLE;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
