| Line 97... |
Line 97... |
// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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input reg_cs ;
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input reg_cs ;
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input reg_wr ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [7:0] reg_wdata ;
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input [3:0] reg_be ;
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input reg_be ;
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// Outputs
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// Outputs
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output [31:0] reg_rdata ;
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output [7:0] reg_rdata ;
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output reg_ack ;
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output reg_ack ;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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| Line 113... |
Line 113... |
//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire sw_rd_en;
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wire sw_rd_en;
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wire sw_wr_en;
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wire sw_wr_en;
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] wr_be ;
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wire wr_be ;
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reg [31:0] reg_rdata ;
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reg [7:0] reg_rdata;
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reg reg_ack ;
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reg reg_ack ;
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wire [31:0] reg_0; // Software_Reg_0
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wire [31:0] spi_ctrl; // Software-Reg_12
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wire [31:0] reg_1; // Software-Reg_1
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wire [7:0] reg_12; // Software-Reg_12
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wire [31:0] reg_2; // Software-Reg_2
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wire [7:0] reg_13; // Software-Reg_13
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wire [31:0] reg_3; // Software-Reg_3
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wire [7:0] reg_14; // Software-Reg_14
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wire [31:0] reg_4; // Software-Reg_4
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wire [7:0] reg_15; // Software-Reg_15
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wire [31:0] reg_5; // Software-Reg_5
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reg [7:0] reg_out;
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wire [31:0] reg_6; // Software-Reg_6
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wire [31:0] reg_7; // Software-Reg_7
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wire [31:0] reg_8; // Software-Reg_8
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wire [31:0] reg_9; // Software-Reg_9
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wire [31:0] reg_10; // Software-Reg_10
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wire [31:0] reg_11; // Software-Reg_11
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wire [31:0] reg_12; // Software-Reg_12
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wire [31:0] reg_13; // Software-Reg_13
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wire [31:0] reg_14; // Software-Reg_14
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wire [31:0] reg_15; // Software-Reg_15
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reg [31:0] reg_out;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Main code starts here
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// Main code starts here
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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| Line 157... |
Line 146... |
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always @ (posedge mclk or negedge reset_n)
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always @ (posedge mclk or negedge reset_n)
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begin : preg_out_Seq
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begin : preg_out_Seq
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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begin
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begin
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reg_rdata [31:0] <= 32'h0000_0000;
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reg_rdata [7:0] <= 8'h00;
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reg_ack <= 1'b0;
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reg_ack <= 1'b0;
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end
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end
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else if (sw_rd_en && !reg_ack)
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else if (sw_rd_en && !reg_ack)
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begin
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begin
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reg_rdata [31:0] <= reg_out [31:0];
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reg_rdata [7:0] <= reg_out [7:0];
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reg_ack <= 1'b1;
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reg_ack <= 1'b1;
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end
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end
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else if (sw_wr_en && !reg_ack)
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else if (sw_wr_en && !reg_ack)
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reg_ack <= 1'b1;
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reg_ack <= 1'b1;
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else
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else
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| Line 214... |
Line 203... |
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always @( *)
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always @( *)
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begin : preg_sel_Com
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begin : preg_sel_Com
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reg_out [31:0] = 32'd0;
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reg_out [7:0] = 8'd0;
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case (sw_addr [3:0])
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case (sw_addr [3:0])
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4'b0000 : reg_out [31:0] = reg_0 [31:0];
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4'b0000 : reg_out [7:0] = spi_ctrl [7:0];
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4'b0001 : reg_out [31:0] = reg_1 [31:0];
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4'b0001 : reg_out [7:0] = spi_ctrl [15:8];
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4'b0010 : reg_out [31:0] = reg_2 [31:0];
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4'b0010 : reg_out [7:0] = spi_ctrl [23:16];
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4'b0011 : reg_out [31:0] = reg_3 [31:0];
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4'b0011 : reg_out [7:0] = spi_ctrl [31:24];
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4'b0100 : reg_out [31:0] = reg_4 [31:0];
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4'b0100 : reg_out [7:0] = cfg_datain [7:0];
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4'b0101 : reg_out [31:0] = reg_5 [31:0];
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4'b0101 : reg_out [7:0] = cfg_datain [15:8];
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4'b0110 : reg_out [31:0] = reg_6 [31:0];
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4'b0110 : reg_out [7:0] = cfg_datain [23:16];
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4'b0111 : reg_out [31:0] = reg_7 [31:0];
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4'b0111 : reg_out [7:0] = cfg_datain [31:24];
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4'b1000 : reg_out [31:0] = reg_8 [31:0];
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4'b1000 : reg_out [7:0] = cfg_dataout [7:0];
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4'b1001 : reg_out [31:0] = reg_9 [31:0];
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4'b1001 : reg_out [7:0] = cfg_dataout [15:8];
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4'b1010 : reg_out [31:0] = reg_10 [31:0];
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4'b1010 : reg_out [7:0] = cfg_dataout [23:16];
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4'b1011 : reg_out [31:0] = reg_11 [31:0];
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4'b1011 : reg_out [7:0] = cfg_dataout [31:24];
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4'b1100 : reg_out [31:0] = reg_12 [31:0];
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4'b1100 : reg_out [7:0] = reg_12 [7:0];
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4'b1101 : reg_out [31:0] = reg_13 [31:0];
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4'b1101 : reg_out [7:0] = reg_13 [7:0];
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4'b1110 : reg_out [31:0] = reg_14 [31:0];
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4'b1110 : reg_out [7:0] = reg_14 [7:0];
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4'b1111 : reg_out [31:0] = reg_15 [31:0];
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4'b1111 : reg_out [7:0] = reg_15 [7:0];
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endcase
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endcase
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end
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end
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Individual register assignments
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// Individual register assignments
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Logic for Register 0 : SPI Control Register
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// Logic for Register 0 : SPI Control Register
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire cfg_op_req = reg_0[31]; // cpu request
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wire cfg_op_req = spi_ctrl[31]; // cpu request
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wire [1:0] cfg_tgt_sel = reg_0[24:23]; // target chip select
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wire [1:0] cfg_tgt_sel = spi_ctrl[24:23]; // target chip select
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wire [1:0] cfg_op_type = reg_0[22:21]; // SPI operation type
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wire [1:0] cfg_op_type = spi_ctrl[22:21]; // SPI operation type
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wire [1:0] cfg_transfer_size = reg_0[20:19]; // SPI transfer size
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wire [1:0] cfg_transfer_size = spi_ctrl[20:19]; // SPI transfer size
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wire [5:0] cfg_sck_period = reg_0[18:13]; // sck clock period
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wire [5:0] cfg_sck_period = spi_ctrl[18:13]; // sck clock period
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wire [4:0] cfg_sck_cs_period = reg_0[12:8]; // cs setup/hold period
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wire [4:0] cfg_sck_cs_period = spi_ctrl[12:8]; // cs setup/hold period
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wire [7:0] cfg_cs_byte = reg_0[7:0]; // cs bit information
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wire [7:0] cfg_cs_byte = spi_ctrl[7:0]; // cs bit information
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generic_register #(8,0 ) u_spi_ctrl_be0 (
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generic_register #(8,0 ) u_spi_ctrl_be0 (
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.we ({8{sw_wr_en_0 &
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.we ({8{sw_wr_en_0 & wr_be }} ),
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wr_be[0] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[7:0] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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//List of Outs
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//List of Outs
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.data_out (reg_0[7:0] )
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.data_out (spi_ctrl[7:0] )
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);
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);
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generic_register #(8,0 ) u_spi_ctrl_be1 (
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generic_register #(8,0 ) u_spi_ctrl_be1 (
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.we ({8{sw_wr_en_0 &
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.we ({8{sw_wr_en_1 & wr_be }} ),
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wr_be[1] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[15:8] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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//List of Outs
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//List of Outs
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.data_out (reg_0[15:8] )
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.data_out (spi_ctrl[15:8] )
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);
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);
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generic_register #(8,0 ) u_spi_ctrl_be2 (
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generic_register #(8,0 ) u_spi_ctrl_be2 (
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.we ({8{sw_wr_en_0 &
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.we ({8{sw_wr_en_2 & wr_be}} ),
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wr_be[2] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[23:16] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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//List of Outs
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//List of Outs
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.data_out (reg_0[23:16] )
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.data_out (spi_ctrl[23:16] )
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);
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);
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assign reg_0[30:24] = 7'h0;
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assign spi_ctrl[30:24] = 7'h0;
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req_register #(0 ) u_spi_ctrl_req (
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req_register #(0 ) u_spi_ctrl_req (
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.cpu_we ({sw_wr_en_0 &
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.cpu_we ({sw_wr_en_3 & wr_be}),
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wr_be[3] } ),
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.cpu_req (reg_wdata[7] ),
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.cpu_req (reg_wdata[31] ),
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.hware_ack (hware_op_done ),
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.hware_ack (hware_op_done ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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//List of Outs
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//List of Outs
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.data_out (reg_0[31] )
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.data_out (spi_ctrl[31] )
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);
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);
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Logic for Register 1 : SPI Data In Register
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// Logic for Register 1 : SPI Data In Register
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire [31:0] cfg_datain = reg_1[31:0];
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generic_register #(8,0 ) u_spi_din_be0 (
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generic_register #(8,0 ) u_spi_din_be0 (
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.we ({8{sw_wr_en_1 &
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.we ({8{sw_wr_en_4 & wr_be }} ),
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wr_be[0] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[7:0] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
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|
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//List of Outs
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//List of Outs
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.data_out (reg_1[7:0] )
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.data_out (cfg_datain[7:0] )
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);
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);
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generic_register #(8,0 ) u_spi_din_be1 (
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generic_register #(8,0 ) u_spi_din_be1 (
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.we ({8{sw_wr_en_1 &
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.we ({8{sw_wr_en_5 & wr_be }} ),
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wr_be[1] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[15:8] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
|
|
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//List of Outs
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//List of Outs
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.data_out (reg_1[15:8] )
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.data_out (cfg_datain[15:8] )
|
);
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);
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generic_register #(8,0 ) u_spi_din_be2 (
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generic_register #(8,0 ) u_spi_din_be2 (
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.we ({8{sw_wr_en_1 &
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.we ({8{sw_wr_en_6 & wr_be }} ),
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wr_be[2] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[23:16] ),
|
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.reset_n (reset_n ),
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.reset_n (reset_n ),
|
.clk (mclk ),
|
.clk (mclk ),
|
|
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//List of Outs
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//List of Outs
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.data_out (reg_1[23:16] )
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.data_out (cfg_datain[23:16] )
|
);
|
);
|
|
|
|
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generic_register #(8,0 ) u_spi_din_be3 (
|
generic_register #(8,0 ) u_spi_din_be3 (
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.we ({8{sw_wr_en_1 &
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.we ({8{sw_wr_en_7 & wr_be }} ),
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wr_be[3] }} ),
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.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[31:24] ),
|
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.reset_n (reset_n ),
|
.reset_n (reset_n ),
|
.clk (mclk ),
|
.clk (mclk ),
|
|
|
//List of Outs
|
//List of Outs
|
.data_out (reg_1[31:24] )
|
.data_out (cfg_datain[31:24] )
|
);
|
);
|
|
|
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//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// Logic for Register 2 : SPI Data output Register
|
// Logic for Register : SPI Data output Register
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
assign reg_2 = cfg_dataout;
|
assign reg_2 = cfg_dataout;
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