URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
[/] [oms8051mini/] [trunk/] [rtl/] [uart/] [uart_core.v] - Diff between revs 6 and 11
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Rev 11 |
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//////////////////////////////////////////////////////////////////////
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//// v-0.0 : NOV 26, 2016 ////
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//// Revision :
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//// 1. initial version picked from ////
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//// v-0.0 : NOV 26, 2016
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// 1. initial version picked from
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//// v-0.1 : NOV 28, 2016 ////
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//// http://www.opencores.org/cores/turbo8051/
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//// 2. Register access correction ////
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//// v-0.1 : NOV 28, 2016
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//// ////
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//// 1. Register access correction
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//// v-0.2 : NOV 28, 2016
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//// 1. Register access changed from 32 bit to 8bit
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////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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input reg_cs ;
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input reg_cs ;
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input reg_wr ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [7:0] reg_wdata ;
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input [3:0] reg_be ;
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input reg_be ;
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// Outputs
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// Outputs
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output [31:0] reg_rdata ;
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output [7:0] reg_rdata ;
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output reg_ack ;
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output reg_ack ;
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// Line Interface
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// Line Interface
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input si ; // uart si
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input si ; // uart si
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output so ; // uart so
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output so ; // uart so
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