//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS 8051 cores UART Interface Module ////
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//// OMS 8051 cores UART Interface Module ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//// v-0.0 : Nov 26, 2016 ////
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//// 1. Initial version picked from ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// Revision :
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//// v-0.0 : Nov 26, 2016
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//// 1. Initial version picked from
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//// http://www.opencores.org/cores/turbo8051/
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//// v-0.1 : Jan 19, 2017
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/// 1. Lint warning fix for case statement //////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// UART rx state machine
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// UART rx state machine
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module uart_rxfsm (
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module uart_rxfsm (
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reset_n ,
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reset_n ,
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baud_clk_16x ,
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baud_clk_16x ,
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cfg_rx_enable ,
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cfg_rx_enable ,
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cfg_stop_bit ,
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cfg_stop_bit ,
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cfg_pri_mod ,
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cfg_pri_mod ,
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error_ind ,
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error_ind ,
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// FIFO control signal
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// FIFO control signal
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fifo_aval ,
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fifo_aval ,
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fifo_wr ,
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fifo_wr ,
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fifo_data ,
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fifo_data ,
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// Line Interface
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// Line Interface
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si
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si
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);
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);
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input reset_n ; // active low reset signal
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input reset_n ; // active low reset signal
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input baud_clk_16x ; // baud clock-16x
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input baud_clk_16x ; // baud clock-16x
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input cfg_rx_enable ; // transmit interface enable
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input cfg_rx_enable ; // transmit interface enable
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input cfg_stop_bit ; // stop bit
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input cfg_stop_bit ; // stop bit
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// 0 --> 1 stop, 1 --> 2 Stop
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// 0 --> 1 stop, 1 --> 2 Stop
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input [1:0] cfg_pri_mod ;// Priority Mode
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input [1:0] cfg_pri_mod ;// Priority Mode
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// 2'b00 --> None
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// 2'b00 --> None
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// 2'b10 --> Even priority
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// 2'b10 --> Even priority
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// 2'b11 --> Odd priority
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// 2'b11 --> Odd priority
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output [1:0] error_ind ; // 2'b00 --> Normal
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output [1:0] error_ind ; // 2'b00 --> Normal
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// 2'b01 --> framing error
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// 2'b01 --> framing error
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// 2'b10 --> parity error
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// 2'b10 --> parity error
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// 2'b11 --> fifo full
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// 2'b11 --> fifo full
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//--------------------------------------
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//--------------------------------------
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// FIFO control signal
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// FIFO control signal
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//--------------------------------------
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//--------------------------------------
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input fifo_aval ; // fifo empty
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input fifo_aval ; // fifo empty
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output fifo_wr ; // fifo write, assumed no back to back write
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output fifo_wr ; // fifo write, assumed no back to back write
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output [7:0] fifo_data ; // fifo write data
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output [7:0] fifo_data ; // fifo write data
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// Line Interface
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// Line Interface
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input si ; // rxd pin
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input si ; // rxd pin
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reg [7:0] fifo_data ; // fifo write data
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reg [7:0] fifo_data ; // fifo write data
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reg fifo_wr ; // fifo write
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reg fifo_wr ; // fifo write
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reg [1:0] error_ind ;
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reg [1:0] error_ind ;
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reg [2:0] cnt ;
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reg [2:0] cnt ;
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reg [3:0] offset ; // free-running counter from 0 - 15
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reg [3:0] offset ; // free-running counter from 0 - 15
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reg [3:0] rxpos ; // stable rx position
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reg [3:0] rxpos ; // stable rx position
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reg [2:0] rxstate ;
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reg [2:0] rxstate ;
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parameter idle_st = 3'b000;
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parameter idle_st = 3'b000;
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parameter xfr_start = 3'b001;
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parameter xfr_start = 3'b001;
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parameter xfr_data_st = 3'b010;
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parameter xfr_data_st = 3'b010;
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parameter xfr_pri_st = 3'b011;
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parameter xfr_pri_st = 3'b011;
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parameter xfr_stop_st1 = 3'b100;
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parameter xfr_stop_st1 = 3'b100;
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parameter xfr_stop_st2 = 3'b101;
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parameter xfr_stop_st2 = 3'b101;
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always @(negedge reset_n or posedge baud_clk_16x) begin
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always @(negedge reset_n or posedge baud_clk_16x) begin
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if(reset_n == 0) begin
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if(reset_n == 0) begin
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rxstate <= 3'b0;
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rxstate <= 3'b0;
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offset <= 4'b0;
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offset <= 4'b0;
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rxpos <= 4'b0;
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rxpos <= 4'b0;
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cnt <= 3'b0;
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cnt <= 3'b0;
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error_ind <= 2'b0;
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error_ind <= 2'b0;
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fifo_wr <= 1'b0;
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fifo_wr <= 1'b0;
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fifo_data <= 8'h0;
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fifo_data <= 8'h0;
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end
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end
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else begin
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else begin
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offset <= offset + 1;
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offset <= offset + 1;
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case(rxstate)
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case(rxstate)
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idle_st : begin
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idle_st : begin
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if(!si) begin // Start indication
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if(!si) begin // Start indication
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if(fifo_aval && cfg_rx_enable) begin
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if(fifo_aval && cfg_rx_enable) begin
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rxstate <= xfr_start;
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rxstate <= xfr_start;
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cnt <= 0;
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cnt <= 0;
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rxpos <= offset + 8; // Assign center rxoffset
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rxpos <= offset + 8; // Assign center rxoffset
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error_ind <= 2'b00;
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error_ind <= 2'b00;
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end
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end
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else begin
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else begin
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error_ind <= 2'b11; // fifo full error indication
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error_ind <= 2'b11; // fifo full error indication
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end
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end
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end else begin
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end else begin
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error_ind <= 2'b00; // Reset Error
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error_ind <= 2'b00; // Reset Error
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end
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end
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end
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end
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xfr_start : begin
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xfr_start : begin
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// Make Sure that minimum 8 cycle low is detected
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// Make Sure that minimum 8 cycle low is detected
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if(cnt < 7 && si) begin // Start indication
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if(cnt < 7 && si) begin // Start indication
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rxstate <= idle_st;
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rxstate <= idle_st;
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end
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end
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else if(cnt == 7 && !si) begin // Start indication
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else if(cnt == 7 && !si) begin // Start indication
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rxstate <= xfr_data_st;
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rxstate <= xfr_data_st;
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cnt <= 0;
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cnt <= 0;
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end else begin
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end else begin
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cnt <= cnt +1;
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cnt <= cnt +1;
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end
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end
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end
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end
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xfr_data_st : begin
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xfr_data_st : begin
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if(rxpos == offset) begin
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if(rxpos == offset) begin
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fifo_data[cnt] <= si;
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fifo_data[cnt] <= si;
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cnt <= cnt+1;
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cnt <= cnt+1;
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if(cnt == 7) begin
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if(cnt == 7) begin
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fifo_wr <= 1;
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fifo_wr <= 1;
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if(cfg_pri_mod == 2'b00) // No Priority
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if(cfg_pri_mod == 2'b00) // No Priority
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rxstate <= xfr_stop_st1;
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rxstate <= xfr_stop_st1;
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else rxstate <= xfr_pri_st;
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else rxstate <= xfr_pri_st;
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end
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end
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end
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end
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end
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end
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xfr_pri_st : begin
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xfr_pri_st : begin
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fifo_wr <= 0;
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fifo_wr <= 0;
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if(rxpos == offset) begin
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if(rxpos == offset) begin
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if(cfg_pri_mod == 2'b10) // even priority
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if(cfg_pri_mod == 2'b10) // even priority
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if( si != ^fifo_data) error_ind <= 2'b10;
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if( si != ^fifo_data) error_ind <= 2'b10;
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else // Odd Priority
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else // Odd Priority
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if( si != ~(^fifo_data)) error_ind <= 2'b10;
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if( si != ~(^fifo_data)) error_ind <= 2'b10;
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rxstate <= xfr_stop_st1;
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rxstate <= xfr_stop_st1;
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end
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end
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end
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end
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xfr_stop_st1 : begin
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xfr_stop_st1 : begin
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fifo_wr <= 0;
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fifo_wr <= 0;
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if(rxpos == offset) begin
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if(rxpos == offset) begin
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if(si) begin
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if(si) begin
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if(cfg_stop_bit) // Two Stop bit
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if(cfg_stop_bit) // Two Stop bit
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rxstate <= xfr_stop_st2;
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rxstate <= xfr_stop_st2;
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else
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else
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rxstate <= idle_st;
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rxstate <= idle_st;
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end else begin // Framing error
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end else begin // Framing error
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error_ind <= 2'b01;
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error_ind <= 2'b01;
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rxstate <= idle_st;
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rxstate <= idle_st;
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end
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end
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end
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end
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end
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end
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xfr_stop_st2 : begin
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xfr_stop_st2 : begin
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if(rxpos == offset) begin
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if(rxpos == offset) begin
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if(si) begin
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if(si) begin
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rxstate <= idle_st;
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rxstate <= idle_st;
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end else begin // Framing error
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end else begin // Framing error
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error_ind <= 2'b01;
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error_ind <= 2'b01;
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rxstate <= idle_st;
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rxstate <= idle_st;
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end
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end
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end
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end
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end
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end
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default: rxstate <= idle_st;
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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