| Line 29... |
Line 29... |
input [7:0] datain;
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input [7:0] datain;
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reg [31:0] read_data;
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reg [31:0] read_data;
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begin
|
begin
|
|
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@(posedge tb_top.app_clk)
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@(posedge tb_top.app_clk)
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tb_top.cpu_write('h2,'h4,{datain,24'h0});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{datain,24'h0});
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tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b0, // Write Operatopm
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2'b0, // Write Operatopm
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2'b0, // Single Transfer
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2'b0, // Single Transfer
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6'h10, // sck clock period
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6'h10, // sck clock period
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5'h2, // cs setup/hold period
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5'h2, // cs setup/hold period
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8'h40 }); // cs bit information
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8'h40 }); // cs bit information
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|
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tb_top.cpu_read('h2,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
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while(read_data[31]) begin
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@(posedge tb_top.app_clk) ;
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@(posedge tb_top.app_clk) ;
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tb_top.cpu_read('h2,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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end
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end
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end
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end
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endtask
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endtask
|
|
|
//***** ST : Write Enable task ******//
|
//***** ST : Write Enable task ******//
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| Line 53... |
Line 53... |
input [31:0] cmd;
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input [31:0] cmd;
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input [7:0] cs_byte;
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input [7:0] cs_byte;
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reg [31:0] read_data;
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reg [31:0] read_data;
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begin
|
begin
|
@(posedge tb_top.app_clk)
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@(posedge tb_top.app_clk)
|
tb_top.cpu_write('h2,'h4,{cmd});
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{cmd});
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tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
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tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
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spi_chip_no[1:0],
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spi_chip_no[1:0],
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2'b0, // Write Operatopm
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2'b0, // Write Operatopm
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2'h3, // 4 Transfer
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2'h3, // 4 Transfer
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6'h10, // sck clock period
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6'h10, // sck clock period
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5'h2, // cs setup/hold period
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5'h2, // cs setup/hold period
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cs_byte[7:0] }); // cs bit information
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cs_byte[7:0] }); // cs bit information
|
|
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tb_top.cpu_read('h2,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
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while(read_data[31]) begin
|
while(read_data[31]) begin
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@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
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tb_top.cpu_read('h2,'h0,read_data);
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tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
| Line 79... |
Line 79... |
input [7:0] cs_byte;
|
input [7:0] cs_byte;
|
reg [31:0] read_data;
|
reg [31:0] read_data;
|
begin
|
begin
|
|
|
@(posedge tb_top.app_clk)
|
@(posedge tb_top.app_clk)
|
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
|
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
|
spi_chip_no[1:0],
|
spi_chip_no[1:0],
|
2'b1, // Read Operatopm
|
2'b1, // Read Operatopm
|
2'h3, // 4 Transfer
|
2'h3, // 4 Transfer
|
6'h10, // sck clock period
|
6'h10, // sck clock period
|
5'h2, // cs setup/hold period
|
5'h2, // cs setup/hold period
|
cs_byte[7:0] }); // cs bit information
|
cs_byte[7:0] }); // cs bit information
|
|
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
|
|
while(read_data[31]) begin
|
while(read_data[31]) begin
|
@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
end
|
end
|
|
|
tb_top.cpu_read('h2,'h8,dataout);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h8,dataout);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
| Line 107... |
Line 107... |
input [23:0] address;
|
input [23:0] address;
|
reg [31:0] read_data;
|
reg [31:0] read_data;
|
begin
|
begin
|
|
|
@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
|
tb_top.cpu_write('h2,'h4,{8'hD8,address[23:0]});
|
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'hD8,address[23:0]});
|
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
|
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
|
spi_chip_no[1:0],
|
spi_chip_no[1:0],
|
2'b0, // Write Operatopm
|
2'b0, // Write Operatopm
|
2'h3, // 4 Transfer
|
2'h3, // 4 Transfer
|
6'h10, // sck clock period
|
6'h10, // sck clock period
|
5'h2, // cs setup/hold period
|
5'h2, // cs setup/hold period
|
8'h1 }); // cs bit information
|
8'h1 }); // cs bit information
|
|
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
|
|
$display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
|
$display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
|
|
|
|
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
while(read_data[31]) begin
|
while(read_data[31]) begin
|
@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
| Line 206... |
Line 206... |
|
|
|
|
task spi_op_over;
|
task spi_op_over;
|
reg [31:0] read_data;
|
reg [31:0] read_data;
|
begin
|
begin
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
while(read_data[31]) begin
|
while(read_data[31]) begin
|
@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
end
|
end
|
#100;
|
#100;
|
end
|
end
|
endtask
|
endtask
|
|
|
| Line 228... |
Line 228... |
|
|
|
|
exit_flag = 1;
|
exit_flag = 1;
|
while(exit_flag == 1) begin
|
while(exit_flag == 1) begin
|
|
|
tb_top.cpu_write('h2,'h4,{8'h05,24'h0});
|
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'h05,24'h0});
|
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
|
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
|
spi_chip_no[1:0],
|
spi_chip_no[1:0],
|
2'b0, // Write Operation
|
2'b0, // Write Operation
|
2'b0, // 1 Transfer
|
2'b0, // 1 Transfer
|
6'h10, // sck clock period
|
6'h10, // sck clock period
|
5'h2, // cs setup/hold period
|
5'h2, // cs setup/hold period
|
8'h0 }); // cs bit information
|
8'h0 }); // cs bit information
|
|
|
|
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
while(read_data[31]) begin
|
while(read_data[31]) begin
|
@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
end
|
end
|
|
|
// Send Status Request Cmd
|
// Send Status Request Cmd
|
|
|
|
|
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
|
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
|
spi_chip_no[1:0],
|
spi_chip_no[1:0],
|
2'b1, // Read Operation
|
2'b1, // Read Operation
|
2'b0, // 1 Transfer
|
2'b0, // 1 Transfer
|
6'h10, // sck clock period
|
6'h10, // sck clock period
|
5'h2, // cs setup/hold period
|
5'h2, // cs setup/hold period
|
8'h40 }); // cs bit information
|
8'h40 }); // cs bit information
|
|
|
|
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
while(read_data[31]) begin
|
while(read_data[31]) begin
|
@(posedge tb_top.app_clk) ;
|
@(posedge tb_top.app_clk) ;
|
tb_top.cpu_read('h2,'h0,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
|
end
|
end
|
|
|
tb_top.cpu_read('h2,'h8,read_data);
|
tb_top.cpu_read(`ADDR_SPACE_SPI,'h8,read_data);
|
exit_flag = read_data[24];
|
exit_flag = read_data[24];
|
$display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
|
$display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
|
repeat (1000) @ (posedge tb_top.app_clk) ;
|
repeat (1000) @ (posedge tb_top.app_clk) ;
|
end
|
end
|
end
|
end
|
