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https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [cpu/] [pipemem.v] - Diff between revs 3 and 32
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| Rev 3 |
Rev 32 |
| Line 50... |
Line 50... |
input [31:0] i_addr;
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input [31:0] i_addr;
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input [31:0] i_data;
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input [31:0] i_data;
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input [4:0] i_oreg;
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input [4:0] i_oreg;
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// CPU outputs
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// CPU outputs
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output wire o_busy;
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output wire o_busy;
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output reg o_pipe_stalled;
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output wire o_pipe_stalled;
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output reg o_valid;
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output reg o_valid;
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output reg o_err;
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output reg o_err;
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output reg [4:0] o_wreg;
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output reg [4:0] o_wreg;
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output reg [31:0] o_result;
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output reg [31:0] o_result;
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// Wishbone outputs
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// Wishbone outputs
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| Line 162... |
Line 162... |
always @(posedge i_clk)
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always @(posedge i_clk)
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// if (i_wb_ack) isn't necessary, since o_valid won't be true
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// if (i_wb_ack) isn't necessary, since o_valid won't be true
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// then either.
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// then either.
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o_result <= i_wb_data;
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o_result <= i_wb_data;
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/*
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assign o_pipe_stalled = (cyc)
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assign o_pipe_stalled = (cyc)
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&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
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&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
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*/
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always @(posedge i_clk)
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o_pipe_stalled <= (i_pipe_stb)&&(cyc)&&(i_wb_stall);
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generate
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generate
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if (IMPLEMENT_LOCK != 0)
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if (IMPLEMENT_LOCK != 0)
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begin
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begin
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reg lock_gbl, lock_lcl;
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reg lock_gbl, lock_lcl;
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