OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [Alu.vhd] - Diff between revs 5 and 8

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 5 Rev 8
Line 1... Line 1...
--! @file
--! @file
--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit
--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit
 
 
--! Use standard library
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
 
use ieee.std_logic_unsigned.all;
 
use ieee.std_logic_arith.all;
 
 
--! Use CPU Definitions package
--! Use CPU Definitions package
library pkgOpenCPU32;
use work.pkgOpenCPU32.all;
 
 
--! ALU is a digital circuit that performs arithmetic and logical operations.
--! ALU is a digital circuit that performs arithmetic and logical operations.
 
 
--! ALU is a digital circuit that performs arithmetic and logical operations. It's the fundamental part of the CPU
--! ALU is a digital circuit that performs arithmetic and logical operations. It's the fundamental part of the CPU
entity Alu is
entity Alu is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);                --! Alu Operand 1
    generic (n : integer := nBits - 1);
           B : in  STD_LOGIC_VECTOR (7 downto 0);                --! Alu Operand 2
         Port ( A : in  STD_LOGIC_VECTOR (n downto 0);           --! Alu Operand 1
           S : out  STD_LOGIC_VECTOR (7 downto 0);               --! Alu Output
           B : in  STD_LOGIC_VECTOR (n downto 0);                --! Alu Operand 2
           sel : in  STD_LOGIC_VECTOR (2 downto 0));     --! Select operation
           S : out  STD_LOGIC_VECTOR (n downto 0);               --! Alu Output
 
           sel : in  aluOps);                                                                   --! Select operation
end Alu;
end Alu;
 
 
--! @brief Architure definition of the ALU
--! @brief Architure definition of the ALU
--! @details More details about this mux element.
--! @details More details about this mux element.
architecture Behavioral of Alu is
architecture Behavioral of Alu is
 
 
begin
begin
 
        --! Behavior description of combinational circuit (Can not infer any FF(Flip flop))
 
        process (A,B,sel) is
 
        begin
 
                case sel is
 
                        when alu_sum =>
 
                                S <= A + B;
 
 
 
                        when alu_sub =>
 
                                S <= A - B;
 
 
 
                        when alu_inc =>
 
                                S <= A - B;
 
 
 
                        when alu_dec =>
 
                                S <= A - B;
 
 
 
                        when alu_and =>
 
                                S <= A and B;
 
 
 
                        when alu_or =>
 
                                S <= A or B;
 
 
 
                        when alu_xor =>
 
                                S <= A xor B;
 
 
 
                        when others =>
 
                                S <= (others => 'Z');
 
                end case;
 
        end process;
 
 
end Behavioral;
end Behavioral;
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.