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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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entity ControlUnit is
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entity ControlUnit is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( reset : in STD_LOGIC;
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : in STD_LOGIC_VECTOR (n downto 0);
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FlagsDp : in STD_LOGIC_VECTOR (n downto 0); --! Flags comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0);
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0);
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0);
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpAluOp : out aluOps; --! Alu operations
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters;
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteEn : out STD_LOGIC;
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileReadAddrA : out generalRegisters;
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrB : out generalRegisters;
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DpRegFileReadAddrB : out generalRegisters; --! General register address to read
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DpRegFileReadEnA : out STD_LOGIC;
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DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
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DpRegFileReadEnB : out STD_LOGIC;
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DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
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MemoryDataRead : out std_logic;
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MemoryDataReadEn : out std_logic; --! Enable Main memory read
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MemoryDataWrite : out std_logic;
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MemoryDataWriteEn: out std_logic; --! Enable Main memory write
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0);
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
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MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0);
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MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory write address
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0));
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
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end ControlUnit;
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end ControlUnit;
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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when initial =>
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when initial =>
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cyclesExecute := 0;
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cyclesExecute := 0;
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PC <= (others => '0');
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PC <= (others => '0');
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IR <= (others => '0');
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IR <= (others => '0');
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MemoryDataAddr <= (others => '0');
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MemoryDataAddr <= (others => '0');
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MemoryDataRead <= '0';
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MemoryDataReadEn <= '0';
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MemoryDataWrite <= '0';
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MemoryDataWriteEn <= '0';
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MemoryDataAddr <= (others => '0');
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MemoryDataAddr <= (others => '0');
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nextCpuState <= fetch;
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nextCpuState <= fetch;
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-- Fetch state (Go to memory and get a instruction)
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-- Fetch state (Go to memory and get a instruction)
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when fetch =>
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when fetch =>
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-- Increment program counter (Remember that PC will be update only on the next cycle...
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-- Increment program counter (Remember that PC will be update only on the next cycle...
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PC <= PC + conv_std_logic_vector(1, nBits);
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PC <= PC + conv_std_logic_vector(1, nBits);
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MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
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MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
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IR <= MemoryDataInput;
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IR <= MemoryDataInput;
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MemoryDataRead <= '1';
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MemoryDataReadEn <= '1';
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nextCpuState <= decode;
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nextCpuState <= decode;
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-- Detect with instruction came from memory, set the number of cycles to execute...
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-- Detect with instruction came from memory, set the number of cycles to execute...
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when decode =>
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when decode =>
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MemoryDataRead <= '0';
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MemoryDataReadEn <= '0';
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MemoryDataWrite <= '0';
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MemoryDataWriteEn <= '0';
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-- The high attribute points to the highes bit position
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-- The high attribute points to the highes bit position
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case opcodeIR is
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case opcodeIR is
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when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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nextCpuState <= execute;
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nextCpuState <= execute;
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