| Line 20... |
Line 20... |
Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
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Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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outEn : in typeEnDis; --! Enable/Disable datapath output
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outEn : in typeEnDis; --! Enable/Disable datapath output
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aluOp : in aluOps; --! Alu operations
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aluOp : in aluOps; --! Alu operations
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muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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| Line 44... |
Line 44... |
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
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D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
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sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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END COMPONENT;
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END COMPONENT;
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--! Component declaration to instantiate the Multiplexer3_1 circuit
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--! Component declaration to instantiate the Multiplexer3_1 circuit
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COMPONENT Multiplexer3_1 is
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COMPONENT Multiplexer3_1 is
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