| Line 34... |
Line 34... |
clk : in STD_LOGIC; --! Main system clock
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpAluOp : out aluOps; --! Alu operations
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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Line 62... |
signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal outEnDp : typeEnDis; --! Wire to connect Test signal to component
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signal outEnDp : typeEnDis; --! Wire to connect Test signal to component
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signal MuxDp : dpMuxInputs; --! Wire to connect Test signal to component
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signal MuxDp : dpMuxInputs; --! Wire to connect Test signal to component
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signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component
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signal MuxRegDp : dpMuxAluIn; --! Wire to connect Test signal to component
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signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal DpAluOp : aluOps; --! Wire to connect Test signal to component
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signal DpAluOp : aluOps; --! Wire to connect Test signal to component
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signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component
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signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component
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signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadAddrA : generalRegisters; --! Wire to connect Test signal to component
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signal DpRegFileReadAddrA : generalRegisters; --! Wire to connect Test signal to component
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
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assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
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assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;
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assert MuxRegDp = fromRegFileA report "Invalid value" severity FAILURE;
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wait for CLK_period; -- Executing ... 1
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wait for CLK_period; -- Executing ... 1
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-- State writing on the registers
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-- State writing on the registers
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assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
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assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
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-- Verify if signals for the datapath are valid
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-- Verify if signals for the datapath are valid
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assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
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assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
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assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
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assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
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assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;
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assert MuxRegDp = fromImediate report "Invalid value" severity FAILURE;
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assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
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wait for CLK_period; -- Executing ... 1
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wait for CLK_period; -- Executing ... 1
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| Line 344... |
Line 344... |
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wait for CLK_period; -- Executing ... 3
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wait for CLK_period; -- Executing ... 3
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wait for CLK_period; -- Executing ... 4
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wait for CLK_period; -- Executing ... 4
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wait for CLK_period; -- Executing ... 4
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--wait for CLK_period; -- Executing ... 4
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-------------------------------------------------------------------------------------------------
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-- jmp 0 (Jump to position 0)--------------------------------------------------------------------
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REPORT "jmp 0" SEVERITY NOTE;
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MemoryDataInput <= jmp_val & conv_std_logic_vector(0,4) & conv_std_logic_vector(0, 22);
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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--wait for CLK_period; -- Executing ... 1
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--assert MemoryDataRdAddr = conv_std_logic_vector(0, 32) report "Invalid value" severity FAILURE;
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--wait for CLK_period; -- Executing ... 2
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-------------------------------------------------------------------------------------------------
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-- jmpr 3 (Jump to position Current + 3)--------------------------------------------------------------------
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REPORT "jmpr 3" SEVERITY NOTE;
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MemoryDataInput <= jmpr_val & conv_std_logic_vector(0,4) & conv_std_logic_vector(3, 22);
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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wait for CLK_period; -- Executing ... 1
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--assert MemoryDataRdAddr = conv_std_logic_vector(3, 32) report "Invalid value" severity FAILURE;
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--wait for CLK_period; -- Executing ... 2
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-------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------
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-- Close file
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-- Close file
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file_close(cmdfile);
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file_close(cmdfile);
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