| Line 270... |
Line 270... |
|
|
//Register input values to be used in CRC assignment logic after crc init stage
|
//Register input values to be used in CRC assignment logic after crc init stage
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
`ifdef RESET_ALL
|
|
if(!res_n) d_in_data_dly <= {DWIDTH{1'b0}};
|
|
else
|
|
`endif
|
|
begin
|
|
d_in_data_dly <= d_in_data;
|
|
end
|
|
|
|
`ifdef RESET_ALL
|
if(!res_n) begin
|
if(!res_n) begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
d_in_lng_per_flit_dly[i_f] <= 4'h0;
|
d_in_lng_per_flit_dly[i_f] <= 4'h0;
|
end
|
end
|
d_in_data_dly <= {DWIDTH{1'b0}};
|
|
d_in_hdr_dly <= {FPW{1'b0}};
|
d_in_hdr_dly <= {FPW{1'b0}};
|
d_in_tail_dly <= {FPW{1'b0}};
|
d_in_tail_dly <= {FPW{1'b0}};
|
d_in_valid_dly <= {FPW{1'b0}};
|
d_in_valid_dly <= {FPW{1'b0}};
|
end else begin
|
end else
|
|
`endif
|
|
begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
d_in_lng_per_flit_dly[i_f] <= d_in_lng_per_flit[i_f];
|
d_in_lng_per_flit_dly[i_f] <= d_in_lng_per_flit[i_f];
|
end
|
end
|
d_in_data_dly <= d_in_data;
|
d_in_hdr_dly <= d_in_hdr & d_in_valid;
|
d_in_hdr_dly <= d_in_hdr;
|
d_in_tail_dly <= d_in_tail & d_in_valid;
|
d_in_tail_dly <= d_in_tail;
|
|
d_in_valid_dly <= d_in_valid;
|
d_in_valid_dly <= d_in_valid;
|
end
|
end
|
end
|
end
|
|
|
//====================================================================
|
//====================================================================
|
//---------------------------------Inter CRC stage, CRC assignment Logic
|
//---------------------------------Inter CRC stage, CRC assignment Logic
|
//====================================================================
|
//====================================================================
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
`ifdef RESET_ALL
|
|
if (!res_n) crc_accu_in[i_f] <= {32{1'b0}};
|
|
else
|
|
`endif
|
|
begin
|
|
crc_accu_in[i_f] <= crc_init_out[i_f];
|
|
end
|
|
end
|
|
|
if(!res_n) begin
|
if(!res_n) begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
crc_accu_in[i_f] <= {32{1'b0}};
|
|
crc_accu_in_valid[i_f] <= {FPW{1'b0}};
|
crc_accu_in_valid[i_f] <= {FPW{1'b0}};
|
crc_accu_in_tail[i_f] <= {FPW{1'b0}};
|
crc_accu_in_tail[i_f] <= {FPW{1'b0}};
|
payload_remain[i_f] <= 4'h0;
|
payload_remain[i_f] <= 4'h0;
|
end
|
end
|
end else begin
|
end else begin
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
crc_accu_in[i_f] <= crc_init_out[i_f];
|
|
crc_accu_in_valid[i_f] <= 4'h0;
|
crc_accu_in_valid[i_f] <= 4'h0;
|
crc_accu_in_tail[i_f] <= 4'h0;
|
crc_accu_in_tail[i_f] <= 4'h0;
|
end
|
end
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
//First go through accu crcs
|
//First go through accu crcs
|
|
|
if(|payload_remain[i_f]) begin
|
if(|payload_remain[i_f]) begin
|
|
|
if(payload_remain[i_f] > FPW) begin
|
if(payload_remain[i_f] > FPW) begin
|
crc_accu_in_valid[i_f] <= {FPW{1'b1}};
|
crc_accu_in_valid[i_f] <= {FPW{1'b1}};
|
payload_remain[i_f] <= payload_remain[i_f]-FPW;
|
payload_remain[i_f] <= payload_remain[i_f]-FPW;
|
| Line 349... |
Line 368... |
//---------------------------------Constant propagation of the data pipeline
|
//---------------------------------Constant propagation of the data pipeline
|
//====================================================================
|
//====================================================================
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
`ifdef ASYNC_RES
|
if(!res_n) begin
|
if(!res_n) begin
|
for(i_c=0;i_c<2;i_c=i_c+1)begin
|
for(i_c=0;i_c<2;i_c=i_c+1)begin
|
crc_data_pipe_in_data[i_c] <= {DWIDTH{1'b0}};
|
crc_data_pipe_in_data[i_c] <= {DWIDTH{1'b0}};
|
|
end
|
|
end else
|
|
`endif
|
|
begin
|
|
//Data forward
|
|
crc_data_pipe_in_data[0] <= d_in_data_dly;
|
|
crc_data_pipe_in_data[1] <= crc_data_pipe_in_data[0];
|
|
end
|
|
|
|
`ifdef RESET_ALL
|
|
if(!res_n) begin
|
|
for(i_c=0;i_c<2;i_c=i_c+1)begin
|
crc_data_pipe_in_hdr[i_c] <= {FPW{1'b0}};
|
crc_data_pipe_in_hdr[i_c] <= {FPW{1'b0}};
|
crc_data_pipe_in_tail[i_c] <= {FPW{1'b0}};
|
crc_data_pipe_in_tail[i_c] <= {FPW{1'b0}};
|
crc_data_pipe_in_valid[i_c] <= {FPW{1'b0}};
|
crc_data_pipe_in_valid[i_c] <= {FPW{1'b0}};
|
end
|
end
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
target_crc_per_tail1[i_f] <= 3'h0;
|
target_crc_per_tail1[i_f] <= 3'h0;
|
end
|
end
|
end else begin
|
end else
|
|
`endif
|
|
begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
target_crc_per_tail1[i_f] <= target_crc_per_tail[i_f];
|
target_crc_per_tail1[i_f] <= target_crc_per_tail[i_f];
|
end
|
end
|
|
|
//Set the first stage of the data pipeline
|
//Set the first stage of the data pipeline
|
crc_data_pipe_in_data[0] <= d_in_data_dly;
|
|
crc_data_pipe_in_hdr[0] <= d_in_hdr_dly;
|
crc_data_pipe_in_hdr[0] <= d_in_hdr_dly;
|
crc_data_pipe_in_tail[0] <= d_in_tail_dly;
|
crc_data_pipe_in_tail[0] <= d_in_tail_dly;
|
crc_data_pipe_in_valid[0] <= d_in_valid_dly;
|
crc_data_pipe_in_valid[0] <= d_in_valid_dly;
|
|
|
//Data Pipeline propagation
|
//Second Stage
|
for(i_c=0;i_c<(1);i_c=i_c+1)begin
|
crc_data_pipe_in_tail[1] <= crc_data_pipe_in_tail[0];
|
crc_data_pipe_in_data[i_c+1] <= crc_data_pipe_in_data[i_c];
|
crc_data_pipe_in_hdr[1] <= crc_data_pipe_in_hdr[0];
|
crc_data_pipe_in_tail[i_c+1] <= crc_data_pipe_in_tail[i_c];
|
crc_data_pipe_in_tail[1] <= crc_data_pipe_in_tail[0];
|
crc_data_pipe_in_hdr[i_c+1] <= crc_data_pipe_in_hdr[i_c];
|
crc_data_pipe_in_valid[1] <= crc_data_pipe_in_valid[0];
|
crc_data_pipe_in_tail[i_c+1] <= crc_data_pipe_in_tail[i_c];
|
|
crc_data_pipe_in_valid[i_c+1] <= crc_data_pipe_in_valid[i_c];
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
//====================================================================
|
//====================================================================
|
//---------------------------------At the end of the data pipeline get and compare the CRCs
|
//---------------------------------At the end of the data pipeline get and compare the CRCs
|
//====================================================================
|
//====================================================================
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
`ifdef ASYNC_RES
|
|
if(!res_n)data_rdy_flit[i_f] <= {128{1'b0}};
|
|
else
|
|
`endif
|
|
begin // Datapath
|
|
data_rdy_flit[i_f] <= crc_data_pipe_out_data_flit[i_f];
|
|
end
|
|
end
|
|
//Propagate
|
|
d_out_hdr <= crc_data_pipe_in_hdr[1];
|
|
d_out_tail <= crc_data_pipe_in_tail[1];
|
|
d_out_valid <= crc_data_pipe_in_valid[1];
|
|
|
if(!res_n) begin
|
if(!res_n) begin
|
|
|
//Reset the outputs
|
//Reset the outputs
|
d_out_hdr <= {FPW{1'b0}};
|
|
d_out_tail <= {FPW{1'b0}};
|
|
d_out_valid <= {FPW{1'b0}};
|
|
d_out_error <= {FPW{1'b0}};
|
d_out_error <= {FPW{1'b0}};
|
d_out_poisoned <= {FPW{1'b0}};
|
d_out_poisoned <= {FPW{1'b0}};
|
d_out_rtc <= {FPW{1'b0}};
|
d_out_rtc <= {FPW{1'b0}};
|
d_out_flow <= {FPW{1'b0}};
|
d_out_flow <= {FPW{1'b0}};
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
data_rdy_flit[i_f] <= {128{1'b0}};
|
|
end
|
|
|
|
end else begin
|
end else begin
|
|
|
d_out_rtc <= {FPW{1'b0}};
|
d_out_rtc <= {FPW{1'b0}};
|
d_out_error <= {FPW{1'b0}};
|
d_out_error <= {FPW{1'b0}};
|
d_out_poisoned <= {FPW{1'b0}};
|
d_out_poisoned <= {FPW{1'b0}};
|
d_out_flow <= {FPW{1'b0}};
|
d_out_flow <= {FPW{1'b0}};
|
|
|
//Propagate
|
|
d_out_hdr <= crc_data_pipe_in_hdr[1];
|
|
d_out_tail <= crc_data_pipe_in_tail[1];
|
|
d_out_valid <= crc_data_pipe_in_valid[1];
|
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
|
|
//Propagate data
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
data_rdy_flit[i_f] <= crc_data_pipe_out_data_flit[i_f];
|
d_out_error[i_f] <= crc_data_pipe_in_hdr[1][i_f] && ( ~|lng(crc_data_pipe_out_data_flit[i_f])
|
|
|| lng(crc_data_pipe_out_data_flit[i_f])>9
|
|
|| !lng_dln_equal(crc_data_pipe_out_data_flit[i_f]));
|
|
|
if(crc_data_pipe_in_tail[1][i_f])begin
|
if(crc_data_pipe_in_tail[1][i_f])begin
|
//Finally compare the CRC and add flow/rtc information if there is a tail
|
//Finally compare the CRC and add flow/rtc information if there is a tail
|
|
|
if(crc(crc_data_pipe_out_data_flit[i_f]) == ~crc_per_flit[target_crc_per_tail1[i_f]]) begin
|
if(crc(crc_data_pipe_out_data_flit[i_f]) == ~crc_per_flit[target_crc_per_tail1[i_f]]) begin
|
| Line 438... |
Line 473... |
if(!crc_data_pipe_in_hdr[1][i_f]) begin
|
if(!crc_data_pipe_in_hdr[1][i_f]) begin
|
//Multi-FLIT packets always have a valid RTC
|
//Multi-FLIT packets always have a valid RTC
|
d_out_rtc[i_f] <= 1'b1;
|
d_out_rtc[i_f] <= 1'b1;
|
end else begin
|
end else begin
|
|
|
if((cmd(crc_data_pipe_out_data_flit[i_f]) == CMD_TRET) || !is_flow(crc_data_pipe_out_data_flit[i_f])) begin
|
if((cmd(crc_data_pipe_out_data_flit[i_f]) == CMD_TRET) || !is_rsp_flow(crc_data_pipe_out_data_flit[i_f])) begin
|
//All non-flow packets have a valid RTC
|
//All non-flow packets have a valid RTC, except TRET
|
d_out_rtc[i_f] <= 1'b1;
|
d_out_rtc[i_f] <= 1'b1;
|
end
|
end
|
if(is_flow(crc_data_pipe_out_data_flit[i_f])) begin
|
if(is_rsp_flow(crc_data_pipe_out_data_flit[i_f])) begin
|
//Set the flow packet indicator
|
|
d_out_flow[i_f] <= 1'b1;
|
d_out_flow[i_f] <= 1'b1;
|
|
|
//Check flow packets zero fields
|
|
if(|adrs(crc_data_pipe_out_data_flit[i_f]) || |tag(crc_data_pipe_out_data_flit[i_f])) begin
|
|
d_out_error[i_f] <= 1'b1;
|
|
end
|
|
if( (cmd(crc_data_pipe_out_data_flit[i_f]) != CMD_TRET) &&
|
|
(|rtc(crc_data_pipe_out_data_flit[i_f]) || |seq(crc_data_pipe_out_data_flit[i_f]))) begin
|
|
d_out_error[i_f] <= 1'b1;
|
|
end
|
|
if((cmd(crc_data_pipe_out_data_flit[i_f]) == CMD_PRET) && |frp(crc_data_pipe_out_data_flit[i_f])) begin
|
|
d_out_error[i_f] <= 1'b1;
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
end
|
end
|
| Line 476... |
Line 498... |
generate
|
generate
|
for(f=0;f<FPW;f=f+1) begin : crc_init_gen
|
for(f=0;f<FPW;f=f+1) begin : crc_init_gen
|
crc_128_init crc_init_I
|
crc_128_init crc_init_I
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
|
`ifdef ASYNC_RES
|
.res_n(res_n),
|
.res_n(res_n),
|
|
`endif
|
.inData(d_in_flit_removed_crc[f]),
|
.inData(d_in_flit_removed_crc[f]),
|
.crc(crc_init_out[f])
|
.crc(crc_init_out[f])
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
| Line 495... |
Line 519... |
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.res_n(res_n),
|
.res_n(res_n),
|
.tail(crc_accu_in_tail[f]),
|
.tail(crc_accu_in_tail[f]),
|
.d_in(crc_accu_in_combined[f]),
|
.d_in(crc_accu_in_combined[f]),
|
.valid(crc_accu_in_valid[f]),
|
|
.crc_out(crc_per_flit[f])
|
.crc_out(crc_per_flit[f])
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule
|
endmodule
|
`default_nettype wire
|
`default_nettype wire
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
