URL
https://opencores.org/ocsvn/openhmc/openhmc/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 11 |
Rev 15 |
| Line 82... |
Line 82... |
//=====================================================================================================
|
//=====================================================================================================
|
wire [LANE_WIDTH-1:0] data_out_tmp;
|
wire [LANE_WIDTH-1:0] data_out_tmp;
|
wire [LANE_WIDTH-1:0] run_length_d_out;
|
wire [LANE_WIDTH-1:0] run_length_d_out;
|
reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
|
reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
|
wire [14:0] lfsr_steps [LANE_WIDTH-1:0]; // LFSR values for serial time steps
|
wire [14:0] lfsr_steps [LANE_WIDTH-1:0]; // LFSR values for serial time steps
|
reg seed_set;
|
|
|
|
// SEQUENTIAL PROCESS
|
// SEQUENTIAL PROCESS
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
`ifdef RESET_ALL
|
if (!res_n) begin
|
if (!res_n) begin
|
seed_set <= 1'b0;
|
|
lfsr[14:0] <= 15'h0;
|
|
data_out <= {LANE_WIDTH {1'b0}};
|
data_out <= {LANE_WIDTH {1'b0}};
|
end
|
end else
|
else
|
`endif
|
begin
|
begin
|
if(!seed_set) begin
|
|
lfsr[14:0] <= seed;
|
|
seed_set <= 1'b1;
|
|
end else begin
|
|
if (disable_scrambler) begin
|
|
lfsr[14:0] <= 15'h0;
|
|
end else begin
|
|
lfsr[14:0] <= lfsr_steps[LANE_WIDTH-1];
|
|
end
|
|
end
|
|
data_out <= run_length_d_out;
|
data_out <= run_length_d_out;
|
end
|
end
|
end // serial shift right with left input
|
|
|
if(!res_n) lfsr <= seed;
|
|
else lfsr <= disable_scrambler ? {15{1'b0}} : lfsr_steps[LANE_WIDTH-1];
|
|
|
|
end
|
|
|
// SCRAMBLE
|
// SCRAMBLE
|
genvar j;
|
genvar j;
|
generate
|
generate
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.