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Line 42... |
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//-- After this works for HMC, generalize for PCIe as well
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//-- After this works for HMC, generalize for PCIe as well
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class axi4_stream_slave_driver #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) extends uvm_driver #(hmc_packet);
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class axi4_stream_slave_driver #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) extends uvm_driver #(hmc_packet);
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axi4_stream_config axi4_stream_cfg;
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axi4_stream_config axi4_stream_cfg;
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rand int block_cycles;
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constraint c_block_cycles {
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soft block_cycles dist{0:/30,[1:5]:/41, [6:15]:/25, [16:10000]:/4};
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}
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virtual interface axi4_stream_if #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)) vif;
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virtual interface axi4_stream_if #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)) vif;
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`uvm_component_param_utils_begin(axi4_stream_slave_driver #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)))
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`uvm_component_param_utils_begin(axi4_stream_slave_driver #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)))
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Line 70... |
if(uvm_config_db#(virtual interface axi4_stream_if #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)))::get(this, "", "vif",vif) ) begin
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if(uvm_config_db#(virtual interface axi4_stream_if #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)))::get(this, "", "vif",vif) ) begin
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this.vif = vif;
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this.vif = vif;
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end else begin
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end else begin
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`uvm_fatal(get_type_name(),"vif is not set")
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`uvm_fatal(get_type_name(),"vif is not set")
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end
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end
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if (!uvm_config_db#(axi4_stream_config)::get(this, "", "axi4_stream_cfg", axi4_stream_cfg)) begin
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uvm_report_fatal(get_type_name(), $psprintf("axi4_stream_cfg not set via config_db"));
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end
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endfunction : build_phase
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endfunction : build_phase
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task run_phase(uvm_phase phase);
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task run_phase(uvm_phase phase);
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bit ready_asserted = 0;
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bit last_valid = 0;
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int set_probability;
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super.run_phase(phase);
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super.run_phase(phase);
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forever begin
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forever begin
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if(vif.ARESET_N !== 1) begin
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if(vif.ARESET_N !== 1) begin
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Line 90... |
end
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end
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fork
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fork
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forever begin
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forever begin
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//-- Accept packets
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//-- Accept packets
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@(negedge vif.ACLK);
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@(posedge vif.ACLK);
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set_probability_randomization : assert (std::randomize(set_probability) with {set_probability >= 0 && set_probability < 10;});
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if(axi4_stream_cfg.open_rsp_mode==UVM_ACTIVE) begin
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vif.TREADY <= 1'b1;
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end else begin
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if (vif.TVALID)
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randcase
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3 : vif.TREADY <= 1;
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1 : vif.TREADY <= 0;
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endcase
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else
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randcase
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1 : vif.TREADY <= 1;
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1 : vif.TREADY <= 0;
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1 : begin //-- hold tready at least until tvalid is set
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vif.TREADY <= 0;
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void'(this.randomize());
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while (vif.TVALID == 0)
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@(posedge vif.ACLK);
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repeat(block_cycles) @(posedge vif.ACLK); //-- wait 2 additional cycles
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//-- Higher probability to be ready when the master has something to send
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if (ready_asserted == 0 && vif.TVALID == 1 && set_probability > 3) begin
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ready_asserted = 1;
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//-- Can be ready when the master has nothing to send
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end else if (ready_asserted == 0 && vif.TVALID == 0 && set_probability > 8) begin
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ready_asserted = 1;
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//-- Only become not ready after accepting something
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end else if (ready_asserted == 1 && vif.TVALID == 1 && set_probability > 3) begin
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ready_asserted = 0;
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end
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end
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endcase
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vif.TREADY <= ready_asserted;
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last_valid = vif.TVALID == 1'b1;
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end
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end
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end
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begin //-- Asynchronous reset
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begin //-- Asynchronous reset
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@(negedge vif.ARESET_N);
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@(negedge vif.ARESET_N);
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end
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end
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join_any
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join_any
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