| Line 46... |
Line 46... |
//-- variables
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//-- variables
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//--
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//--
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rand int hmc_tokens;
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rand int hmc_tokens;
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rand int rx_tokens;
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rand int rx_tokens;
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rand bit [5:0] bit_slip_time;
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rand bit [2:0] cube_id;
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rand bit [2:0] cube_id;
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rand bit cfg_tx_lane_reverse;
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rand bit cfg_tx_lane_reverse;
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rand bit [15:0] cfg_hsstx_inv;
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rand bit [15:0] cfg_hsstx_inv;
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rand bit cfg_scram_enb;
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bit cfg_scram_enb = 1;
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rand bit [15:0] cfg_tx_lane_delay[16] = '{16{4'h0}};
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rand bit [15:0] cfg_tx_lane_delay[16];
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rand bit [ 3:0] cfg_retry_limit = 3; //-- LINKRETRY - infinite retry when cfg_retry_limit[3] == 1
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rand bit [ 3:0] cfg_retry_limit = 3; //-- LINKRETRY - infinite retry when cfg_retry_limit[3] == 1
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rand bit [ 2:0] cfg_retry_timeout = 5;
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rand bit [ 2:0] cfg_retry_timeout = 5;
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rand bit cfg_check_pkt = 1; //-- check for valid packet
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rand bit cfg_check_pkt = 1; //-- check for valid packet
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bit cfg_lane_auto_correct = 1;
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bit cfg_lane_auto_correct = 1;
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bit cfg_rsp_open_loop = 0;
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uvm_active_passive_enum cfg_rsp_open_loop = UVM_PASSIVE;
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int cfg_rx_clk_ratio = 40;
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bit cfg_half_link_mode_rx = (`LOG_NUM_LANES==3);
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bit cfg_half_link_mode_rx = (2**`LOG_NUM_LANES==8);
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bit [7:0] cfg_tx_rl_lim = 85;
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bit [7:0] cfg_tx_rl_lim = 85;
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int cfg_tx_clk_ratio = 40;
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`ifdef HMC_12G
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bit cfg_half_link_mode_tx = (2**`LOG_NUM_LANES==8);
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int cfg_rx_clk_ratio = 50; //Set to 50 for 12.5Gbit , 60 for 15Gbit
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bit [7:0] cfg_init_retry_rxcnt = 16;
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int cfg_tx_clk_ratio = 50; //Set to 50 for 12.5Gbit , 60 for 15Gbit
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bit [7:0] cfg_init_retry_txcnt = 6; //-- Actual value in BFM is 4times this value
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`else
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int cfg_rx_clk_ratio = 40; //Set to 50 for 12.5Gbit , 60 for 15Gbit
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int cfg_tx_clk_ratio = 40; //Set to 50 for 12.5Gbit , 60 for 15Gbit
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`endif
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bit cfg_half_link_mode_tx = (`LOG_NUM_LANES==3);
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rand bit [7:0] cfg_init_retry_rxcnt;
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rand bit [7:0] cfg_init_retry_txcnt; //-- Actual value in BFM is 4times this value
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realtime cfg_tsref = 1us;
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realtime cfg_tsref = 1us;
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realtime cfg_top = 1us;
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realtime cfg_top = 1us;
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bit cfg_retry_enb = 1;
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bit cfg_retry_enb = 1;
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| Line 80... |
Line 86... |
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//--
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//--
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//-- constrains
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//-- constrains
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//--
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//--
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constraint cfg_init_retry_rxcnt_c {
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cfg_init_retry_rxcnt == 16;
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// cfg_init_retry_rxcnt <= 20;
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}
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constraint cfg_init_retry_txcnt_c {
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//Actual Value is constraint*4
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// cfg_init_retry_txcnt >= 5;
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cfg_init_retry_txcnt == 7;
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}
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constraint bit_slip_time_c {
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bit_slip_time >= 32;
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bit_slip_time <= 63;
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}
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constraint hmc_tokens_c {
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constraint hmc_tokens_c {
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hmc_tokens >= 25;
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hmc_tokens >= 25;
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soft hmc_tokens dist{[25:30]:/5, [31:100]:/15, [101:1023]:/80};
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// soft hmc_tokens dist{[25:30]:/5, [31:100]:/15, [101:1023]:/80};
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soft hmc_tokens dist{[25:30]:/5, [31:219]:/95}; //Current hardware
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}
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}
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constraint cfg_hsstx_inv_c {
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constraint cfg_hsstx_inv_c {
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cfg_hsstx_inv >= 0;
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cfg_hsstx_inv >= 0;
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}
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}
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constraint rx_tokens_c {
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constraint rx_tokens_c {
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rx_tokens >= 9;
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rx_tokens >= 9;
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soft rx_tokens dist{[9:30]:/5, [31:100]:/15, [101:1023]:/80};
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// soft rx_tokens dist{[9:30]:/5, [31:100]:/15, [101:1023]:/80}; //Make sure to increase the input buffer accordingly
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soft rx_tokens dist{[9:30]:/5, [31:255]:/95}; //Safe value for input buffer address size = 8. Leave some FLITs for poisoned packets
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}
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}
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constraint cube_id_c {
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constraint cube_id_c {
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cube_id >= 0;
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cube_id >= 0;
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soft cube_id == 0;
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soft cube_id == 0;
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| Line 111... |
Line 135... |
cfg_retry_timeout == 7;
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cfg_retry_timeout == 7;
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}
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}
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constraint error_rates_c {
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constraint error_rates_c {
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soft cfg_rsp_dln == 5;
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soft cfg_rsp_dln ==0;//dist{[0:10]};
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soft cfg_rsp_lng == 5;
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soft cfg_rsp_lng ==0;//dist{[0:10]};
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soft cfg_rsp_crc == 5;
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soft cfg_rsp_crc ==0;//dist{[0:10]};
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soft cfg_rsp_seq == 5;
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soft cfg_rsp_seq ==0;//dist{[0:10]};
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soft cfg_rsp_poison == 5;
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soft cfg_rsp_poison ==0;//dist{[0:10]};
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soft cfg_req_dln ==0;//dist{[0:10]};
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soft cfg_req_dln == 5;
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soft cfg_req_lng ==0;//dist{[0:10]};
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soft cfg_req_lng == 5;
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soft cfg_req_crc ==0;//dist{[0:10]};
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soft cfg_req_crc == 5;
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soft cfg_req_seq == 0; // Must be zero for BFM 28965 !
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soft cfg_req_seq == 0; // Must be zero for BFM 28965 !
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(
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(
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cfg_rsp_dln ||
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cfg_rsp_dln ||
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cfg_rsp_lng ||
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cfg_rsp_lng ||
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cfg_rsp_crc ||
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cfg_rsp_crc ||
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cfg_rsp_seq ||
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cfg_rsp_seq ||
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| Line 159... |
Line 181... |
super.do_print(printer);
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super.do_print(printer);
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endfunction : do_print
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endfunction : do_print
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endclass : hmc_link_config
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endclass : hmc_link_config
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`endif // AXI4_STREAM_CONFIG_SV
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`endif // HMC_LINK_CONFIG_SV
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`endif // HMC_LINK_CONFIG_SV
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`endif // HMC_LINK_CONFIG_SV
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