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Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 192 $
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// $Rev: 200 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2013-12-17 21:15:28 +0100 (Tue, 17 Dec 2013) $
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// $LastChangedDate: 2015-01-21 23:01:31 +0100 (Wed, 21 Jan 2015) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 347... |
Line 347... |
omsp_execution_unit execution_unit_0 (
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omsp_execution_unit execution_unit_0 (
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// OUTPUTs
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// OUTPUTs
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.cpuoff (cpuoff), // Turns off the CPU
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.cpuoff (cpuoff), // Turns off the CPU
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.gie (gie), // General interrupt enable
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.mab (eu_mab), // Memory address bus
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.mab (eu_mab), // Memory address bus
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.mb_en (eu_mb_en), // Memory bus enable
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.mb_en (eu_mb_en), // Memory bus enable
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.mb_wr (eu_mb_wr), // Memory bus write transfer
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.mb_wr (eu_mb_wr), // Memory bus write transfer
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.mdb_out (eu_mdb_out), // Memory data bus output
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.mdb_out (eu_mdb_out), // Memory data bus output
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.oscoff (oscoff), // Turns off LFXT1 clock input
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| Line 363... |
Line 364... |
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
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.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
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.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
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.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
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.e_state (e_state), // Execution state
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.e_state (e_state), // Execution state
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.exec_done (exec_done), // Execution completed
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.exec_done (exec_done), // Execution completed
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.gie (gie), // General interrupt enable
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_alu (inst_alu), // ALU control signals
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.inst_alu (inst_alu), // ALU control signals
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
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.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
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