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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 193 and 200

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 193 and 200

Rev 193	Rev 200
Line 347...	Line 347...
`omsp_execution_unit execution_unit_0 (`	`omsp_execution_unit execution_unit_0 (`

`// OUTPUTs`	`// OUTPUTs`
`.cpuoff (cpuoff), // Turns off the CPU`	`.cpuoff (cpuoff), // Turns off the CPU`
`.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input`	`.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input`
	`.gie (gie), // General interrupt enable`
`.mab (eu_mab), // Memory address bus`	`.mab (eu_mab), // Memory address bus`
`.mb_en (eu_mb_en), // Memory bus enable`	`.mb_en (eu_mb_en), // Memory bus enable`
`.mb_wr (eu_mb_wr), // Memory bus write transfer`	`.mb_wr (eu_mb_wr), // Memory bus write transfer`
`.mdb_out (eu_mdb_out), // Memory data bus output`	`.mdb_out (eu_mdb_out), // Memory data bus output`
`.oscoff (oscoff), // Turns off LFXT1 clock input`	`.oscoff (oscoff), // Turns off LFXT1 clock input`
Line 363...	Line 364...
`.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU`	`.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU`
`.dbg_mem_dout (dbg_mem_dout), // Debug unit data output`	`.dbg_mem_dout (dbg_mem_dout), // Debug unit data output`
`.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write`	`.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write`
`.e_state (e_state), // Execution state`	`.e_state (e_state), // Execution state`
`.exec_done (exec_done), // Execution completed`	`.exec_done (exec_done), // Execution completed`
`.gie (gie), // General interrupt enable`
`.inst_ad (inst_ad), // Decoded Inst: destination addressing mode`	`.inst_ad (inst_ad), // Decoded Inst: destination addressing mode`
`.inst_as (inst_as), // Decoded Inst: source addressing mode`	`.inst_as (inst_as), // Decoded Inst: source addressing mode`
`.inst_alu (inst_alu), // ALU control signals`	`.inst_alu (inst_alu), // ALU control signals`
`.inst_bw (inst_bw), // Decoded Inst: byte width`	`.inst_bw (inst_bw), // Decoded Inst: byte width`
`.inst_dest (inst_dest), // Decoded Inst: destination (one hot)`	`.inst_dest (inst_dest), // Decoded Inst: destination (one hot)`