| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 136 $
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// $Rev: 204 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
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// $LastChangedDate: 2015-07-08 22:34:10 +0200 (Wed, 08 Jul 2015) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_TA_NO_INCLUDE
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`ifdef OMSP_TA_NO_INCLUDE
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`else
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`else
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`include "omsp_timerA_defines.v"
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`include "omsp_timerA_defines.v"
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`endif
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`endif
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| Line 232... |
Line 232... |
if (puc_rst) tacctl0 <= 16'h0000;
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if (puc_rst) tacctl0 <= 16'h0000;
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else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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|
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wire cci0;
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wire cci0;
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wire cci0_s;
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reg scci0;
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reg scci0;
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wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0};
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wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0_s, 3'h0};
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// TACCR0 Register
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// TACCR0 Register
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//------------------
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//------------------
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reg [15:0] taccr0;
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reg [15:0] taccr0;
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| Line 264... |
Line 265... |
if (puc_rst) tacctl1 <= 16'h0000;
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if (puc_rst) tacctl1 <= 16'h0000;
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else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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wire cci1;
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wire cci1;
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wire cci1_s;
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reg scci1;
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reg scci1;
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wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0};
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wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1_s, 3'h0};
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// TACCR1 Register
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// TACCR1 Register
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//------------------
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//------------------
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reg [15:0] taccr1;
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reg [15:0] taccr1;
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| Line 296... |
Line 298... |
if (puc_rst) tacctl2 <= 16'h0000;
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if (puc_rst) tacctl2 <= 16'h0000;
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else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
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else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
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else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
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else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
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wire cci2;
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wire cci2;
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wire cci2_s;
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reg scci2;
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reg scci2;
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wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0};
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wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2_s, 3'h0};
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// TACCR2 Register
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// TACCR2 Register
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//------------------
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//------------------
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reg [15:0] taccr2;
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reg [15:0] taccr2;
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| Line 471... |
Line 474... |
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
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assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
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(tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
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(tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
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(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
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(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
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// CCIx synchronization
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// CCIx synchronization
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wire cci0_s;
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wire cci1_s;
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wire cci2_s;
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omsp_sync_cell sync_cell_cci0 (
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omsp_sync_cell sync_cell_cci0 (
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.data_out (cci0_s),
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.data_out (cci0_s),
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.data_in (cci0),
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.data_in (cci0),
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.clk (mclk),
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.clk (mclk),
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.rst (puc_rst)
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.rst (puc_rst)
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