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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 472 and 552

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Rev 472	Rev 552
Line 46...	Line 46...
`#include "opcode/or32.h"`	`#include "opcode/or32.h"`
`#include "dmmu.h"`	`#include "dmmu.h"`
`#include "immu.h"`	`#include "immu.h"`
`#include "execute.h"`	`#include "execute.h"`

`#if DYNAMIC_EXECUTION`
`#include "dyn-rec.h"`
`#endif`


`/! Global temporary variable to increase speed. /`	`/! Global temporary variable to increase speed. /`
`struct dev_memarea *cur_area;`	`struct dev_memarea *cur_area;`

`/* Glboal variables set by MMU if cache inhibit bit is set for current`	`/* Glboal variables set by MMU if cache inhibit bit is set for current`
`access. */`	`access. */`
Line 559...	Line 554...

`if (config.sim.mprofile)`	`if (config.sim.mprofile)`
`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`	`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`

`phys_memaddr = memaddr;`	`phys_memaddr = memaddr;`
`#if !(DYNAMIC_EXECUTION)`
`phys_memaddr = immu_translate (memaddr);`	`phys_memaddr = immu_translate (memaddr);`

`if (except_pending)`	`if (except_pending)`
`return 0;`	`return 0;`
`#endif`

`if (config.debug.enabled)`	`if (config.debug.enabled)`
`*breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);`	`*breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);`

`if ((NULL != ic_state) && ic_state->enabled)`	`if ((NULL != ic_state) && ic_state->enabled)`
Line 729...	Line 722...
`{`	`{`
`cur_vadd = vaddr;`	`cur_vadd = vaddr;`
`runtime.sim.mem_cycles += mem->ops.delayw;`	`runtime.sim.mem_cycles += mem->ops.delayw;`
`mem->ops.writefunc32 (memaddr & mem->size_mask, value,`	`mem->ops.writefunc32 (memaddr & mem->size_mask, value,`
`mem->ops.write_dat32);`	`mem->ops.write_dat32);`
`#if DYNAMIC_EXECUTION`
`dyn_checkwrite (memaddr);`
`#endif`
`}`	`}`
`else`	`else`
`{`	`{`
`if (config.sim.report_mem_errs)`	`if (config.sim.report_mem_errs)`
`{`	`{`
Line 761...	Line 751...
`{`	`{`
`cur_vadd = vaddr;`	`cur_vadd = vaddr;`
`runtime.sim.mem_cycles += mem->ops.delayw;`	`runtime.sim.mem_cycles += mem->ops.delayw;`
`mem->ops.writefunc16 (memaddr & mem->size_mask, value,`	`mem->ops.writefunc16 (memaddr & mem->size_mask, value,`
`mem->ops.write_dat16);`	`mem->ops.write_dat16);`
`#if DYNAMIC_EXECUTION`
`dyn_checkwrite (memaddr);`
`#endif`
`}`	`}`
`else`	`else`
`{`	`{`
`if (config.sim.report_mem_errs)`	`if (config.sim.report_mem_errs)`
`{`	`{`
Line 793...	Line 780...
`{`	`{`
`cur_vadd = vaddr;`	`cur_vadd = vaddr;`
`runtime.sim.mem_cycles += mem->ops.delayw;`	`runtime.sim.mem_cycles += mem->ops.delayw;`
`mem->ops.writefunc8 (memaddr & mem->size_mask, value,`	`mem->ops.writefunc8 (memaddr & mem->size_mask, value,`
`mem->ops.write_dat8);`	`mem->ops.write_dat8);`
`#if DYNAMIC_EXECUTION`
`dyn_checkwrite (memaddr);`
`#endif`
`}`	`}`
`else`	`else`
`{`	`{`
`if (config.sim.report_mem_errs)`	`if (config.sim.report_mem_errs)`
`{`	`{`

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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 472 and 552