OpenCores
URL https://opencores.org/ocsvn/ourisc/ourisc/trunk

Subversion Repositories ourisc

[/] [ourisc/] [trunk/] [rtl/] [packages/] [opcodes.vhd] - Diff between revs 4 and 12

Show entire file | Details | Blame | View Log

Rev 4 Rev 12
Line 1... Line 1...
 
----------------------------------------------------------------------------------
 
-- Engineer: Joao Carlos Nunes Bittencourt
 
----------------------------------------------------------------------------------
 
-- Create Date:    13:18:18 03/06/2012 
 
----------------------------------------------------------------------------------
 
-- Design Name:    Opcode Package
 
-- Package Name:   flags
 
----------------------------------------------------------------------------------
 
-- Project Name:   16-bit uRISC Processor
 
----------------------------------------------------------------------------------
 
-- Revision: 
 
--      1.0 - File Created
 
--      2.0 - Project refactoring
--
--
--      Package File Template
----------------------------------------------------------------------------------
--
 
--      Purpose: This package defines supplemental types, subtypes, 
 
--               constants, and functions 
 
--
 
--   To use any of the example code shown below, uncomment the lines and modify as necessary
 
--
 
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
package Operations is
package operations is
        constant add:            std_logic_vector (4 downto 0) := "00000";
        constant add:            std_logic_vector (4 downto 0) := "00000";
        constant addinc:         std_logic_vector (4 downto 0) := "00001";
        constant addinc:         std_logic_vector (4 downto 0) := "00001";
        constant inca:           std_logic_vector (4 downto 0) := "00011";
        constant inca:           std_logic_vector (4 downto 0) := "00011";
        constant subdec:         std_logic_vector (4 downto 0) := "00100";
        constant subdec:         std_logic_vector (4 downto 0) := "00100";
        constant sub:            std_logic_vector (4 downto 0) := "00101";
        constant sub:            std_logic_vector (4 downto 0) := "00101";
Line 35... Line 41...
        constant ornotb:         std_logic_vector (4 downto 0) := "11101";
        constant ornotb:         std_logic_vector (4 downto 0) := "11101";
        constant lnand:          std_logic_vector (4 downto 0) := "11110"; -- Logic NAND
        constant lnand:          std_logic_vector (4 downto 0) := "11110"; -- Logic NAND
        constant ones:           std_logic_vector (4 downto 0) := "11111";
        constant ones:           std_logic_vector (4 downto 0) := "11111";
        constant lcl:            std_logic_vector (4 downto 0) := "00010"; -- Load constant low
        constant lcl:            std_logic_vector (4 downto 0) := "00010"; -- Load constant low
        constant lch:            std_logic_vector (4 downto 0) := "00111"; -- Load constant high
        constant lch:            std_logic_vector (4 downto 0) := "00111"; -- Load constant high
end Operations;
end operations;
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.