| Line 165... |
Line 165... |
|
|
signal bp0_data : std_logic_vector( 31 downto 0 );
|
signal bp0_data : std_logic_vector( 31 downto 0 );
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Declare Global SYS_CON stuff:
|
-- Declare Global SYS_CON stuff:
|
signal s_core_clk_out : std_logic;
|
signal clk : std_logic;
|
signal s_reset_out : std_logic;
|
signal reset : std_logic;
|
signal s_dcm_rst_out : std_logic;
|
signal dcm_rst : std_logic;
|
|
signal reset_p : std_logic;
|
|
signal reset_p_z1 : std_logic;
|
|
signal reset_p_z2 : std_logic;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
begin
|
begin
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Instantiate CORE64_M6 module with PB BUS:
|
-- Instantiate CORE64_M6 module with PB BUS:
|
| Line 198... |
Line 201... |
|
|
pcie_lstatus => pcie_lstatus,
|
pcie_lstatus => pcie_lstatus,
|
pcie_link_up => pcie_link_up,
|
pcie_link_up => pcie_link_up,
|
|
|
---- Локальная шина ----
|
---- Локальная шина ----
|
clk_out => s_core_clk_out, -- S6 PCIE x1 module clock output
|
clk_out => clk, -- S6 PCIE x1 module clock output
|
reset_out => s_reset_out, --
|
reset_out => reset, --
|
dcm_rstp => s_dcm_rst_out, -- S6 PCIE x1 module INV trn_reset_n_c
|
dcm_rstp => dcm_rst, -- S6 PCIE x1 module INV trn_reset_n_c
|
|
|
---- BAR1 (PB bus) ----
|
---- BAR1 (PB bus) ----
|
aclk => s_core_clk_out, -- !!! same clock as clk_out
|
aclk => clk, -- !!! same clock as clk_out
|
aclk_lock => '1', --
|
aclk_lock => '1', --
|
pb_master => pb_master, --
|
pb_master => pb_master, --
|
pb_slave => pb_slave, --
|
pb_slave => pb_slave, --
|
|
|
---- BAR0 (to PE_MAIN) - блоки управления ----
|
---- BAR0 (to PE_MAIN) - блоки управления ----
|
| Line 237... |
Line 240... |
BLOCK_CNT => x"0008" -- число блоков управления
|
BLOCK_CNT => x"0008" -- число блоков управления
|
)
|
)
|
port map
|
port map
|
(
|
(
|
---- Global ----
|
---- Global ----
|
reset_hr1 => s_reset_out, -- 0 - сброс
|
reset_hr1 => reset, -- 0 - сброс
|
clk => s_core_clk_out, -- Тактовая частота PCIE x1 S6
|
clk => clk, -- Тактовая частота PCIE x1 S6
|
pb_reset => pb_reset, -- 0 - сброс ведомой ПЛИС
|
pb_reset => pb_reset, -- 0 - сброс ведомой ПЛИС
|
|
|
---- HOST ----
|
---- HOST ----
|
bl_adr => bp_adr( 4 downto 0 ), -- адрес
|
bl_adr => bp_adr( 4 downto 0 ), -- адрес
|
bl_data_in => bp_host_data, -- данные
|
bl_data_in => bp_host_data, -- данные
|
| Line 251... |
Line 254... |
|
|
---- Управление ----
|
---- Управление ----
|
brd_mode => brd_mode -- регистр BRD_MODE
|
brd_mode => brd_mode -- регистр BRD_MODE
|
|
|
);
|
);
|
|
|
|
|
|
reset_p <= (not reset) or (not brd_mode(3));
|
|
reset_p_z1 <= reset_p after 1 ns when rising_edge( clk );
|
|
reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk );
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Instantiate PB BUS <-> WB BUS translator module:
|
-- Instantiate PB BUS <-> WB BUS translator module:
|
--
|
--
|
PW_WB : core64_pb_wishbone
|
PW_WB : core64_pb_wishbone
|
port map
|
port map
|
(
|
(
|
reset => s_dcm_rst_out, --! 1 - сброс
|
reset => reset_p_z2, --! 1 - сброс
|
clk => s_core_clk_out, --! тактовая частота локальной шины
|
clk => clk, --! тактовая частота локальной шины
|
|
|
---- BAR1 ----
|
---- BAR1 ----
|
pb_master => pb_master, --! запрос
|
pb_master => pb_master, --! запрос
|
pb_slave => pb_slave, --! ответ
|
pb_slave => pb_slave, --! ответ
|
|
|
| Line 287... |
Line 296... |
);
|
);
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Module Output route:
|
-- Module Output route:
|
--
|
--
|
o_wb_clk <= s_core_clk_out; -- route from PW_WB wrk clock
|
o_wb_clk <= clk; -- route from PW_WB wrk clock
|
--
|
--
|
o_wb_rst <= s_dcm_rst_out; -- convert to POSITIVE LOGIC
|
|
|
pr_o_wb_rst: process( reset_p, clk ) begin
|
|
if( reset_p='1' ) then
|
|
o_wb_rst <= '1' after 1 ns;
|
|
elsif( rising_edge( clk ) ) then
|
|
o_wb_rst <= reset_p_z2 after 1 ns;
|
|
end if;
|
|
end process;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end pcie_core64_wishbone;
|
end pcie_core64_wishbone;
|
|
|
No newline at end of file
|
No newline at end of file
|
