| Line 47... |
Line 47... |
-- PART OF THIS FILE AT ALL TIMES.
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_axi_basic_rx_pipeline.vhd
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-- File : cl_a7pcie_x4_axi_basic_rx_pipeline.vhd
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-- Version : 1.10
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-- Version : 1.11
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--
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--
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-- Description:
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-- Description:
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-- TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI.
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-- TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI.
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--
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--
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-- Notes:
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-- Notes:
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| Line 119... |
Line 119... |
);
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);
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END cl_a7pcie_x4_axi_basic_rx_pipeline;
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END cl_a7pcie_x4_axi_basic_rx_pipeline;
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ARCHITECTURE trans OF cl_a7pcie_x4_axi_basic_rx_pipeline IS
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ARCHITECTURE trans OF cl_a7pcie_x4_axi_basic_rx_pipeline IS
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SIGNAL is_sof : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL is_sof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
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SIGNAL is_sof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL is_sof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
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SIGNAL is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
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SIGNAL is_eof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL is_eof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
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SIGNAL reg_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
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SIGNAL reg_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
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SIGNAL tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
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SIGNAL tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
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SIGNAL tkeep_prev : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
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SIGNAL tkeep_prev : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
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SIGNAL reg_tlast : STD_LOGIC;
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SIGNAL reg_tlast : STD_LOGIC:= '0';
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SIGNAL rsrc_rdy_filtered : STD_LOGIC;
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SIGNAL rsrc_rdy_filtered : STD_LOGIC:= '0';
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SIGNAL trn_rd_DW_swapped : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL trn_rd_DW_swapped : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
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SIGNAL trn_rd_prev : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL trn_rd_prev : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
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SIGNAL data_hold : STD_LOGIC;
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SIGNAL data_hold : STD_LOGIC:= '0';
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SIGNAL data_prev : STD_LOGIC;
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SIGNAL data_prev : STD_LOGIC:= '0';
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SIGNAL trn_reof_prev : STD_LOGIC;
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SIGNAL trn_reof_prev : STD_LOGIC:= '0';
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SIGNAL trn_rrem_prev : STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0);
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SIGNAL trn_rrem_prev : STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0):= (others => '0');
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SIGNAL trn_rsrc_rdy_prev : STD_LOGIC;
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SIGNAL trn_rsrc_rdy_prev : STD_LOGIC:= '0';
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SIGNAL trn_rsrc_dsc_prev : STD_LOGIC;
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SIGNAL trn_rsrc_dsc_prev : STD_LOGIC:= '0';
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SIGNAL trn_rsof_prev : STD_LOGIC;
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SIGNAL trn_rsof_prev : STD_LOGIC:= '0';
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SIGNAL trn_rbar_hit_prev : STD_LOGIC_VECTOR(6 DOWNTO 0);
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SIGNAL trn_rbar_hit_prev : STD_LOGIC_VECTOR(6 DOWNTO 0):= (others => '0');
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SIGNAL trn_rerrfwd_prev : STD_LOGIC;
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SIGNAL trn_rerrfwd_prev : STD_LOGIC:= '0';
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SIGNAL trn_recrc_err_prev : STD_LOGIC;
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SIGNAL trn_recrc_err_prev : STD_LOGIC:= '0';
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|
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-- Null packet handling signals
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-- Null packet handling signals
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SIGNAL null_mux_sel : STD_LOGIC;
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SIGNAL null_mux_sel : STD_LOGIC:= '0';
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SIGNAL trn_in_packet : STD_LOGIC;
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SIGNAL trn_in_packet : STD_LOGIC:= '0';
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SIGNAL dsc_flag : STD_LOGIC;
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SIGNAL dsc_flag : STD_LOGIC:= '0';
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SIGNAL dsc_detect : STD_LOGIC;
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SIGNAL dsc_detect : STD_LOGIC:= '0';
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SIGNAL reg_dsc_detect : STD_LOGIC;
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SIGNAL reg_dsc_detect : STD_LOGIC:= '0';
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SIGNAL trn_rsrc_dsc_d : STD_LOGIC;
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SIGNAL trn_rsrc_dsc_d : STD_LOGIC:= '0';
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|
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-- Declare intermediate signals for referenced outputs
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-- Declare intermediate signals for referenced outputs
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SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
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SIGNAL m_axis_rx_tvalid_xhdl2 : STD_LOGIC;
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SIGNAL m_axis_rx_tvalid_xhdl2 : STD_LOGIC:= '0';
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SIGNAL m_axis_rx_tuser_xhdl1 : STD_LOGIC_VECTOR(21 DOWNTO 0);
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SIGNAL m_axis_rx_tuser_xhdl1 : STD_LOGIC_VECTOR(21 DOWNTO 0):= (others => '0');
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SIGNAL trn_rdst_rdy_xhdl4 : STD_LOGIC;
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SIGNAL trn_rdst_rdy_xhdl4 : STD_LOGIC:= '0';
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SIGNAL mrd_lower : STD_LOGIC;
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SIGNAL mrd_lower : STD_LOGIC:= '0';
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SIGNAL mrd_lk_lower : STD_LOGIC;
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SIGNAL mrd_lk_lower : STD_LOGIC:= '0';
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SIGNAL io_rdwr_lower : STD_LOGIC;
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SIGNAL io_rdwr_lower : STD_LOGIC:= '0';
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SIGNAL cfg_rdwr_lower : STD_LOGIC;
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SIGNAL cfg_rdwr_lower : STD_LOGIC:= '0';
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SIGNAL atomic_lower : STD_LOGIC;
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SIGNAL atomic_lower : STD_LOGIC:= '0';
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SIGNAL np_pkt_lower : STD_LOGIC;
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SIGNAL np_pkt_lower : STD_LOGIC:= '0';
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SIGNAL mrd_upper : STD_LOGIC;
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SIGNAL mrd_upper : STD_LOGIC:= '0';
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SIGNAL mrd_lk_upper : STD_LOGIC;
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SIGNAL mrd_lk_upper : STD_LOGIC:= '0';
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SIGNAL io_rdwr_upper : STD_LOGIC;
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SIGNAL io_rdwr_upper : STD_LOGIC:= '0';
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SIGNAL cfg_rdwr_upper : STD_LOGIC;
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SIGNAL cfg_rdwr_upper : STD_LOGIC:= '0';
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SIGNAL atomic_upper : STD_LOGIC;
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SIGNAL atomic_upper : STD_LOGIC:= '0';
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SIGNAL np_pkt_upper : STD_LOGIC;
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SIGNAL np_pkt_upper : STD_LOGIC:= '0';
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SIGNAL pkt_accepted : STD_LOGIC;
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SIGNAL pkt_accepted : STD_LOGIC:= '0';
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SIGNAL reg_np_counter : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL reg_np_counter : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
|
|
|
BEGIN
|
BEGIN
|
-- Drive referenced outputs
|
-- Drive referenced outputs
|
M_AXIS_RX_TDATA <= m_axis_rx_tdata_xhdl0;
|
M_AXIS_RX_TDATA <= m_axis_rx_tdata_xhdl0;
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M_AXIS_RX_TVALID <= m_axis_rx_tvalid_xhdl2;
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M_AXIS_RX_TVALID <= m_axis_rx_tvalid_xhdl2;
|
