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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_eq.v
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// File : cl_a7pcie_x4_pipe_eq.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_eq.v
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// Filename : pipe_eq.v
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// Description : PIPE Equalization Module for 7 Series Transceiver
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// Description : PIPE Equalization Module for 7 Series Transceiver
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// Version : 20.1
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// Version : 20.1
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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output [ 5:0] EQ_RXEQ_FSM
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output [ 5:0] EQ_RXEQ_FSM
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);
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);
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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reg [ 1:0] txeq_control_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
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reg [ 3:0] txeq_preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
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reg [ 5:0] txeq_deemph_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
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reg [ 1:0] txeq_control_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
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reg [ 3:0] txeq_preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
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reg [ 5:0] txeq_deemph_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
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reg [ 1:0] rxeq_control_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
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reg [ 2:0] rxeq_preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
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reg [ 5:0] rxeq_lffs_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
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reg [ 3:0] rxeq_txpreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
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reg rxeq_user_en_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
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reg [17:0] rxeq_user_txcoeff_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
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reg rxeq_user_mode_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
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reg [ 1:0] rxeq_control_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
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reg [ 2:0] rxeq_preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
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reg [ 5:0] rxeq_lffs_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
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reg [ 3:0] rxeq_txpreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
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reg rxeq_user_en_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
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reg [17:0] rxeq_user_txcoeff_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
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reg rxeq_user_mode_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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reg [18:0] txeq_preset = 19'd0;
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reg [18:0] txeq_preset = 19'd0;
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reg txeq_preset_done = 1'd0;
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reg txeq_preset_done = 1'd0;
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reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
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reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
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