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Line 47... |
// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_wrapper.v
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// File : cl_a7pcie_x4_pipe_wrapper.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_wrapper.v
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// Filename : pipe_wrapper.v
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// Description : PIPE Wrapper for 7 Series Transceiver
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// Description : PIPE Wrapper for 7 Series Transceiver
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// Version : 20.1
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// Version : 20.2
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//---------- PIPE Wrapper Hierarchy --------------------------------------------
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//---------- PIPE Wrapper Hierarchy --------------------------------------------
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// pipe_wrapper.v
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// pipe_wrapper.v
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// pipe_clock.v
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// pipe_clock.v
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| Line 336... |
Line 336... |
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
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output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
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);
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);
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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reg reset_n_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
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reg reset_n_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
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//---------- PIPE Clock Module Output ------------------
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//---------- PIPE Clock Module Output ------------------
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wire clk_pclk;
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wire clk_pclk;
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wire clk_rxusrclk;
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wire clk_rxusrclk;
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wire [PCIE_LANE-1:0] clk_rxoutclk;
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wire [PCIE_LANE-1:0] clk_rxoutclk;
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| Line 742... |
Line 742... |
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
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.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
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.RST_DRP_X16 (rst_drp_x16),
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.RST_DRP_X16 (rst_drp_x16),
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.RST_USERRDY (rst_userrdy),
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.RST_USERRDY (rst_userrdy),
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.RST_TXSYNC_START (rst_txsync_start),
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.RST_TXSYNC_START (rst_txsync_start),
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.RST_IDLE (rst_idle),
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.RST_IDLE (rst_idle),
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.RST_FSM (rst_fsm)
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.RST_FSM (rst_fsm[4:0])
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);
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);
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//---------- Default ---------------------------------------------------
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//---------- Default ---------------------------------------------------
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assign gtp_rst_qpllreset = 1'd0;
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assign gtp_rst_qpllreset = 1'd0;
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| Line 806... |
Line 806... |
assign qrst_ovrd = 1'd0;
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assign qrst_ovrd = 1'd0;
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assign qrst_drp_start = 1'd0;
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assign qrst_drp_start = 1'd0;
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assign qrst_qpllreset = 1'd0;
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assign qrst_qpllreset = 1'd0;
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assign qrst_qpllpd = 1'd0;
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assign qrst_qpllpd = 1'd0;
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assign qrst_idle = 1'd0;
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assign qrst_idle = 1'd0;
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assign qrst_fsm = 1;
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assign qrst_fsm = 4'd1;
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end
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end
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endgenerate
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endgenerate
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